Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
102
The Master and Slave are each capable of exchanging a byte of data during a sequence of
eight clock cycles. In both Master and Slave SPI devices, data is shifted on one edge of the
SCK and is sampled on the opposite edge where data is stable. Edge polarity is determined
by the SPI phase and polarity control.
Slave Select
The active Low Slave Select (SS) input signal is used to select a Slave SPI device. SS
must be Low prior to all data communication to and from the Slave device. SS must stay
Low for the full duration of each character transferred. The SS signal may stay Low dur-
ing the transfer of multiple characters or may deassert between each character.
When the SPI on the Z8F640x family device is configured as the only Master in an SPI
system, the SS pin can be set as either an input or an output. For communication between
the Z8F640x family device SPI Master and external Slave devices, the SS signal, as an
output, can assert the SS input pin on one of the Slave devices. Other GPIO output pins
can also be employed to select external SPI Slave devices.
When the SPI on the Z8F640x family device is configured as one Master in a multi-master
SPI system, the SS pin on the should be set as an input. The SS input signal on the Master
must be High. If the SS signal goes Low (indicating another Master is driving the SPI
bus), a Mode Fault error flag is set in the SPI Status register.
SPI Clock Phase and Polarity Control
The SPI supports four combinations of serial clock phase and polarity using two bits in the
SPI Control register. The clock polarity bit, CLKPOL, selects an active high or active low
clock and has no effect on the transfer format. Table 59 lists the SPI Clock Phase and
Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamen-
tally different transfer formats. For proper data transmission, the clock phase and polarity
must be identical for the SPI Master and the SPI Slave. The Master always places data on
the MOSI line a half-cycle before the clock edge (SCK signal), in order for the Slave to
latch the data.
Table 59. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
SCK
Transmit
Edge
SCK
Receive
Edge
SCK
Idle
State
PHASE
CLKPOL
0
0
1
1
0
1
0
1
Falling
Rising
Rising
Falling
Rising
Falling
Falling
Rising
Low
High
Low
High
PS017610-0404
Serial Peripheral Interface
ZILOG [ ZILOG, INC. ]
