Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
x
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Z8F640x Family Part Selection Guide . . . . . . . . . . . . . . . . 2
Z8F640x Family Package Options . . . . . . . . . . . . . . . . . . . 6
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Characteristics of the Z8F640x family . . . . . . . . . . . . 15
Z8F640x Family Program Memory Maps . . . . . . . . . . . . . 18
Z8F640x Family Data Memory Maps . . . . . . . . . . . . . . . . 19
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . 20
Reset and STOP Mode Recovery Characteristics
and Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9.
Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . 26
Table 10. STOP Mode Recovery Sources and Resulting Action . . . 29
Table 11. Port Availability by Device and Package Type . . . . . . . . . 33
Table 12. Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . 35
Table 13. Port A-H GPIO Address Registers (PxADDR) . . . . . . . . . 37
Table 14. GPIO Port Registers and Sub-Registers . . . . . . . . . . . . . . 37
Table 15. Port A-H Control Registers (PxCTL) . . . . . . . . . . . . . . . . 38
Table 16. Port A-H Data Direction Sub-Registers . . . . . . . . . . . . . . . 39
Table 17. Port A-H Alternate Function Sub-Registers . . . . . . . . . . . 39
Table 18. Port A-H Output Control Sub-Registers . . . . . . . . . . . . . . 40
Table 19. Port A-H High Drive Enable Sub-Registers . . . . . . . . . . . 41
Table 20. Port A-H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . 42
Table 21. Port A-H STOP Mode Recovery Source Enable
Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. Port A-H Output Data Register (PxOUT) . . . . . . . . . . . . . 43
Table 23. Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . 45
Table 24. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . 48
Table 25. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . 49
Table 26. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . 50
Table 27. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . 51
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . 51
Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . 52
Table 30. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . 52
Table 31. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . 53
PS017610-0404
List of Tables
ZILOG [ ZILOG, INC. ]
