Z8 Encore! XP® F08xA Series
Product Specification
178
Table 115. Rotate and Shift Instructions
Mnemonic
SRL
Operands
dst
Instruction
Shift Right Logical
Swap Nibbles
SWAP
dst
eZ8 CPU Instruction Summary
Table 116 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
.
Table 116. eZ8 CPU Instruction Summary
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
ADC dst, src
dst ← dst + src + C
12
13
14
15
16
17
18
19
02
03
04
05
06
07
08
09
*
*
*
*
0
*
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
r
Ir
R
R
R
IR
IM
IM
ER
IM
r
R
IR
ER
ER
r
ADCX dst, src
ADD dst, src
dst ← dst + src + C
dst ← dst + src
*
*
*
*
*
*
*
*
0
0
*
*
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ADDX dst, src
Flags Notation:
dst ← dst + src
*
*
*
*
0
*
* = Value is a function of the result of the operation.
– = Unaffected
0 = Reset to 0
1 = Set to 1
X = Undefined
PS024705-0405
P R E L I M I N A R Y
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
