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Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® F08xA Series  
Product Specification  
158  
On-Chip Debugger Control Register Definitions  
OCD Control Register  
The OCD Control register controls the state of the On-Chip Debugger. This register is  
used to enter or exit DEBUG mode and to enable the BRKinstruction. It can also reset the  
Z8 Encore! XP® F08xA Series device.  
A reset and stop function can be achieved by writing 81Hto this register. A reset and go  
function can be achieved by writing 41Hto this register. If the device is in DEBUG mode,  
a run function can be implemented by writing 40H to this register.  
.
Table 99. OCD Control Register (OCDCTL)  
BITS  
7
6
5
4
3
2
1
0
DBGMODE BRKEN DBGACK  
Reserved  
RST  
FIELD  
RESET  
R/W  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R
R
R
R
R/W  
DBGMODE—Debug Mode  
The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU  
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is  
automatically set when a BRK instruction is decoded and Breakpoints are enabled. If the  
Flash Read Protect Option Bit is enabled, this bit can only be cleared by resetting the  
device. It cannot be written to 0.  
0 = The Z8 Encore! XP® F08xA Series device is operating in NORMAL mode.  
1 = The Z8 Encore! XP® F08xA Series device is in DEBUG mode.  
BRKEN—Breakpoint Enable  
This bit controls the behavior of the BRKinstruction (opcode 00H). By default, Break-  
points are disabled and the BRKinstruction behaves similar to an NOP instruction. If this  
bit is 1, when a BRKinstruction is decoded, the DBGMODEbit of the OCDCTL register is  
automatically set to 1.  
0 = Breakpoints are disabled.  
1 = Breakpoints are enabled.  
DBGACK—Debug Acknowledge  
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a  
Debug Acknowledge character (FFH) to the host when a Breakpoint occurs.  
0 = Debug Acknowledge is disabled.  
1 = Debug Acknowledge is enabled.  
Reserved—Must be 0.  
RST—Reset  
Setting this bit to 1 resets the Z8 Encore! XP® F08xA Series device. The device goes  
PS024705-0405  
P R E L I M I N A R Y  
On-Chip Debugger  
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