Z8 Encore! XP® 4K Series
Product Specification
73
the Timer Output pin changes state (from Low to High or from High to Low) upon Com-
pare.
If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting.
The steps for configuring a timer for COMPARE mode and initiating the count are as fol-
lows:
1. Write to the Timer Control register to:
–
–
–
–
Disable the timer
Configure the timer for COMPARE mode.
Set the prescale value.
Set the initial logic level (High or Low) for the Timer Output alternate function, if
appropriate.
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control register to enable the timer and initiate counting.
In Compare mode, the system clock always provides the timer input. The Compare time
can be calculated by the following equation:
(Compare Value – Start Value) × Prescale
Compare Mode Time (s) = ------------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
GATED Mode
In GATED mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOLbit in the Timer Control register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOLbit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the Reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001Hand counting resumes (assuming the Timer Input signal remains asserted).
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
The steps for configuring a timer for GATED mode and initiating the count are as follows:
PS022815-0206
Timers
ZILOG [ ZILOG, INC. ]
