Z8 Encore! XP® 4K Series
Product Specification
183
the Watch-Dog Timer failure can be detected. A very slow system clock results in very
slow detection times.
It is possible to disable the clock failure detection circuitry as well as all functioning
clock sources. In this case, the Z8 Encore! XP® 4K Series device ceases functioning and
can only be recovered by Power-On-Reset.
Caution:
Oscillator Control Register Definitions
Oscillator Control Register
The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry and selects the primary oscillator,
which becomes the system clock.
The Oscillator Control Register must be unlocked before writing. Writing the two step
sequence E7Hfollowed by 18Hto the Oscillator Control Register unlocks it. The register
is locked at successful completion of a register write to the OSCCTL.
Table 112. Oscillator Control Register (OSCCTL)
BITS
7
6
5
4
3
2
1
0
INTEN
XTLEN
WDTEN
SOFEN
WDFEN
SCKSEL
FIELD
RESET
R/W
1
0
1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F86H
ADDR
INTEN—Internal Precision Oscillator Enable
1 = Internal precision oscillator is enabled
0 = Internal precision oscillator is disabled
XTLEN—Crystal Oscillator Enable; this setting overrides the GPIO register control for
PA0 and PA1
1 = Crystal oscillator is enabled
0 = Crystal oscillator is disabled
WDTEN—Watchdog Timer Oscillator Enable
1 = Watch-Dog Timer oscillator is enabled
0 = Watch-Dog Timer oscillator is disabled
SOFEN—System Clock Oscillator Failure Detection Enable
1 = Failure detection and recovery of system clock oscillator is enabled
0 = Failure detection and recovery of system clock oscillator is disabled
PS022815-0206
Oscillator Control
ZILOG [ ZILOG, INC. ]
