Z86017/Z16017 PCMCIA Interface Solution
Product Specification
75
Table 58. Bus Control Register: Address 2Fh (Continued)
Bit Placement Bit Name
Description
Bit 3
EN_MAP_IO_MEM
When this bit is set, all memory accesses are mapped to
ATA_HIOR and ATA_HIOW. When it is cleared, all
memory accesses are mapped to ATA_MRD and
ATA_MWR.
Bit 5-4
Bit 7-6
DUECE_WIDTH
These bits set the ATA_HIOR/HIOW strobe width and are
clocked by PC_MCLK_IN /2. At Power-On Reset, they
default to 00.
DUECE_ACCESS_DLY
These bits set the ATA_HIOR/HIOW access delay and are
clocked by PC_MCLK_IN /2. At Power-On Reset, they
default to 00.
The ATA_HIOR/HIOW strobe width is three cycles minimum
(PC_MCLK_IN /2), plus IOCHRDY time (if any), plus width count
programmed in bits 5, 4 (Table 59).
Table 59. Strobe Width and Access Delay1
Bits
Bits
7
6
5
4
Delay
Width
7
6
5
4
Delay
Width
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
1
2
3
0
1
2
3
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
2
2
3
3
3
3
0
1
2
3
0
1
2
3
NOTES:
1. Each count equals PC_MCLK_IN /2.
Programming Internal Registers
PS012002-1201
ZILOG [ ZILOG, INC. ]
