Z86017/Z16017 PCMCIA Interface Solution
Product Specification
46
EEPROM Register
Address: SELECT 04h
Name: Interface Configuration Register 3
Type: Read/Write
Table 20. Interface Configuration Register 3: Address 04h
Bit Placement Bit Name
Description
Enables IDE/PCMCIA access to primary task file
addresses 1F<0-7>. This bit is active when set to 1. On
Power-On Reset, this bit is set to 0.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
SEL_PRIMARY_1x
SEL_PRINARY_3x
SEL_SECOND_1x
SEL_SECOND_3x
STR_RST
Enables IDE/PCMCIA access to primary task file
addresses 3F<6-7>. Active when set to 1. On Power-On
Reset, this bit is set to 0 (Table 21).
Enables IDE/PCMCIA access to secondary task file
addresses 17<0-7>. Active when set to 1. On Power-On
Reset, this bit is set to 0.
Enables IDE/PCMCIA access to secondary task file
addresses 37<0-7>. Active when set to 1. On Power-On
Reset, this bit is set to 0.
Switching this bit from Low to High to Low again forces
the ZX6017 to check the level on PC_ATA/HOE pin and
latch the mode. This bit is active when set to 1. On Power-
On Reset, this bit is set to 0.
Bit 5
Bit 6
Bit 7
EN_DIS_RST
Disable PCMCIA reset. This bit is active when set to 1.
Resets from the PCMCIA bus are not allowed. On Power-
On Reset, this bit is set to 0 (Table 22).
EN_PDIAG_INT
EN_PDIAG_EXT
When this bit is set to 1, PDIAG is generated internally. On
Power-On Reset, this bit is set to 0. Also see Registers 02h
and 07h (Table 14 and Table 26).
When this bit is set to 1, PDIAG is generated externally
through the AT_PDIAG pin on the local AT side. On
Power-On Reset, this bit is set to 0. Also see Registers 02h
and 07h (Table 14 and Table 26).
PS012002-1201
Programming Internal Registers
ZILOG [ ZILOG, INC. ]
