Z86017/Z16017 PCMCIA Interface Solution
Product Specification
5
PCMCIA Bus
Local Peripheral Bus
ATA_DATA 15:0
PC_DATA 15:0
Z86017
ATA_HCS0
ATA_HCS1
Chip Selects
Attribute
Memory
PC_HA 10:0
ATA_HA0
ATA_HA1
Address Selects
ATA_HA2
Window 1
PC_RDY//BSY/IREQ/HINT
PC_WAIT/IOCHRDY
PC_HCE1/HCS0
PC_HCE2/HCS1
PC_ATA/HOE
PC_HIOR
PC_HIOW
PC_HWE
PC_REG/DACK
PC_HRESET/HRESET
Start/Range
Decoder
ATA_HIOR
ATA_HIOW
I/O R/W
Strobes
General
Peripheral
Bus Interface
PCMCIA
Host
Window 2
Start/Range
Decoder
Memory R/W
Strobes
ATA_MRD
ATA_MWR
ATA_IOCHRDY
ATA_IREQ
ATA_IOCS16
ATA_RESET
ATA_DREQ/BVD1
Window 3
Start/Range
Decoder
ATA_PDASP/EXTP_WP
ATA_PDIAG/ATA_BHE/RING_IN
ATA_DACK/BVD2
ATA/IDE
Window
Decoder
PC_BVD1/STSCHG/PDIAG
PC_WP/IOIS16/IOCS16
PC_BVD2/SPKR/DASP/DREQ
PC_INPACK/DREQ
EXTP_PWDN
EXTP_AUDIO
CLK
EEPROM or µP
EXTP_STSCHG/RES2
Control
PC_MCLK_IN
POR
POR
EE_CS
EE_SK
µ
0.1
F
EE_DI
EE_MASTER
EE_DO
M_PINT
CS CK DO DI
EEPROM
GND ORG NC VCC
Figure 2. Serial Port Master Mode Control
Serial Port Operation (SLAVE) Mode
When the ZX6017 is placed in serial port SLAVE mode (EE_Master
signal grounded on POR), the EEPROM sequencer is disabled and the
user must provide external hardware (microprocessor) with serial
interface to program CCRs and attribute memory. Additionally, if the
PCMCIA Interface Overview
PS012002-1201
ZILOG [ ZILOG, INC. ]
