Z8018x Family
MPU User Manual
65
Packages not containing an A19 pin or situations using TOUT
instead of A18 yield an address capable of only addressing 512K
of physical space.
Note:
Interrupts
The Z8X180 CPU has twelve interrupt sources, 4 external and 8 internal,
with fixed priority. (Reference Figure 31.)
This section explains the CPU registers associated with interrupt
processing, the TRAP interrupt, interrupt response modes, and the
external interrupts. The detailed discussion of internal interrupt
generation (except TRAP) is presented in the appropriate hardware
section (that is, PRT, DMAC, ASCI, and CSI/O).
(1) TRAP (Undefined Op Code Trap)
(2) NMI (Non Maskable Interrupt)
(3) INT0 (Maskable Interrupt Level 0)
(4) INT1 (Maskable Interrupt Level 1)
(5) INT2 (Maskable Interrupt Level 2)
Higher
Priority
Internal Interrupt
External Interrupt
(6) Timer 0
(7) Timer 1
(8) DMA channel 0
(9) DMA channel 1
Internal Interrupt
(10) Clocked Serial I/O Port
(11) Asynchronous SCI channel 0
(12) Asynchronous SCI channel 1
Lower
Priority
Figure 31. Interrupt Sources
Interrupt Control Registers and Flags. The Z8X180 has three registers and
two flags which are associated with interrupt processing.
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
