Z8018x Family
MPU User Manual
194
Table 31. Z8S180 AC Characteristics (Continued) V = 5V ±10% or
DD
V
= 3.3V ±10%; 33-MHz Characteristics Apply Only to 5V
DD
Z8S180—20
MHz
Z8S180—33
MHz
No.
Symbol Item
Min
Max Min
Max
Unit
13
14
15
16
17
18
19
20
21
22
23
24
25
26
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PHI Fall to RD Rise Delay
PHI Rise to M1 Rise Delay
Data Read Set-up Time
—
—
10
0
25
40
—
—
30
30
—
—
35
25
25
—
25
—
—
—
5
15
15
—
—
15
15
—
—
20
15
15
—
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RDD2
M1D2
DRS
Data Read Hold Time
0
DRH
STD1
STD2
WS
PHI Fall to ST Fall Delay
PHI Fall to ST Rise Delay
WAIT Set-up Time to PHI Fall
WAIT Hold Time from PHI Fall
PHI Rise to Data Float Delay
PHI Rise to WR Fall Delay
PHI Fall to Write Data Delay Time
—
—
15
10
—
—
—
—
—
10
5
WH
—
—
—
10
—
45
WDZ
WRD1
WDD
WDS
WRD2
WRP
Write Data Set-up Time to WR Fall 10
PHI Fall to WR Rise Delay
—
80
WR Pulse Width (Memory Write
Cycle)
26a
27
WR Pulse Width (I/O Write Cycle) 150
Write Data Hold Time from WR Rise 10
—
—
25
70
5
—
—
15
ns
ns
ns
t
t
WDH
IOD1
28
PHI Fall to IORQ Fall Delay IOC
= 1
—
—
PHI Rise to IORQ Fall Delay IOC —
= 0
25
—
15
29
30
31
32
t
t
t
t
PHI Fall to IORQ Rise Delay
M1 Fall to IORQ Fall Delay
INT Set-up Time to PHI Fall
INT Hold Time from PHI Fall
—
25
—
—
—
—
80
15
10
15
—
—
—
ns
ns
ns
ns
IOD2
IOD3
INTS
INTH
125
20
10
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
