Z8018x Family
MPU User Manual
124
Bit
Position Bit/Field R/W
Value Description
Framing Error — If a receive data byte frame is
4
FE
R
delimited by an invalid stop bit (that is, 0, should be 1),
FE is set to 1. FE is cleared to 0 when the EFR bit (Error
Flag Reset) of CNTLA is written to 0, when DCD0 is
High, in IOSTOP mode, and during RESET.
3
RIE
R/W
Receive Interrupt Enable — RIE must be set to 1 to
enable ASCI receive interrupt requests. When RIE is 1, if
any of the flags RDRF, OVRN, PE, or FE become set to
1, an interrupt request is generated. For channel 0, an
interrupt is also generated by the transition of the external
DCD0 input from Low to High.
2
1
CTS1E
TDRE
R/W
Channel 1 CTS Enable — Channel 1 has an external
CTS1 input which is multiplexed with the receive data
pin (RXS) for the CSI/O (Clocked Serial I/O Port).
Setting CTS1E to 1 selects the CTS1 function and
clearing CTS1E to 0 selects the RXS function.
R
Transmit Data Register Empty — TDRE = 1 indicates
that the TDR is empty and the next transmit data byte is
written to TDR. After the byte is written to TDR, TDRE
is cleared to 0 until the ASCI transfers the byte from TDR
to the TSR and then TDRE is again set to 1. TDRE is set
to 1 in IOSTOP mode and during RESET. When the
external CTS input is High, TDRE is reset to 0.
0
TIE
R/W
Transmit Interrupt Enable — TIE must be set to 1 to
enable ASCI transmit interrupt requests. If TIE is 1, an
interrupt is requested when TDRE is 1. TIE is cleared to 0
during RESET.
UM005001-ZMP0400
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