Z02215
Single Chip Modem with Integrated Controller, Data Pump, and AFE
11
PIDR is the data register for transmitting and receiving data, including the AT com-
mands.
In RECEIVE DATA mode (when HRD, HCS, HA0, S/P are Low), Z02215 reads
the data on the Host Parallel Data bus (HD0–HD7) for the external host to read
the contents.
In TRANSMIT DATA mode (when HWR, HCS, HA0, S/P are Low), Z02215 reads
the contents placed on the Host Parallel Data bus (HD0–HD7) by the external
host processor.
PISR is the Status register. Bits 0, 1, 6 and 7 of this register are defined in hard-
ware, and bits 2, 3, 4, and 5 are defined in software as follows:
Table 2. Status Register
7
6
5
4
3
2
1
0
RRIE
R/W
0
TRIE
R/W
0
DCD
R/W
1
RBRK
R/W
0
DTR
R/W
0
SBRK
R/W
0
RRF
R/W
0
TRE
R/W
1
Default
Value
Bit No.
Mnemonic R/W
Description
Bit 7
RRIE
TRIE
DCD
R/W
R/W
R/W
0
0
1
Receive Register Interrupt Enable. When this bit is 1, the
Z02215 drives the HIRQ pin Low when RRF is 1.
Bit 6
Bit 5
Transmit Register Interrupt Enable. When this bit is 1, the
Z02215 drives the HIRQ pin Low when TRE is 1
DCD signal sent from the Z02215.
1–Active
0–Inactive
Bit 4
RBRK
R/W
0
Break signal sent to the host. The Z02215 sets this bit to 1
to indicate that a line break is transmitted to the host. The
Z02215 resets this bit to 0 when the line break condition is
ended.
Bit 3
Bit 2
DTR
R/W
R/W
0
0
DTR signal sent to the Z02215.
1: Active
0: Inactive
SBRK
Send Line Break to the Z02215. The host sets this bit to 1
to transmit a line break to the Z02215. The host sets this bit
to 0 to stop transmitting a line break. The host performs the
timing of the transmitted line break.
Bit 1
Bit 0
RRF
TRE
R/W
R/W
0
1
Receive Register Full. The host can receive a byte from the
Z02215 when this bit is 1.
Transmit Register Empty. The host can transmit a byte to
the Z02215 when this bit is 1.
PS001907-0904
Parallel Host Interface
ZILOG [ ZILOG, INC. ]
