eZ80L92 MCU
Product Specification
20
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol
Function
Signal Direction
Description
94
PB6
GPIO Port B
Bidirectional
This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or
open-source output.
MISO
PB7
Master In
Slave Out
Bidirectional
Bidirectional
The MISO line is configured as an input
when the eZ80L92 MCU is an SPI master
device and as an output when eZ80L92
MCU is an SPI slave device. This signal is
multiplexed with PB6.
95
GPIO Port B
This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or
open-source output.
MOSI
Master Out
Slave In
Bidirectional
The MOSI line is configured as an output
when the eZ80L92 MCU is an SPI master
device and as an input when the eZ80L92
MCU is an SPI slave device. This signal is
multiplexed with PB7.
96
97
98
99
V
V
Power Supply
Power Supply.
Ground.
DD
SS
Ground
2
2
SDA
SCL
I C Serial Data Bidirectional
This pin carries the I C data signal.
2
I C Serial
Clock
Bidirectional
This pin is used to receive and transmit
2
the I C clock.
100
PHI
System Clock Output
This pin is an output driven by the internal
system clock.
PS013014-0107
Architectural Overview
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