AN47
If the PWM frequency is higher than approximately 10kHz and the duty cycle above the specified
minimum value, the device will remain active and the output will be continuous, with a nominal
output current given by:
0.1 D
PWM
-
I
OUT
≈
-------------------------
R
S
[for 0.16< D
PWM
<1]
ADJ
PWM
ZXLD1350
GND
GND
Input buffer transistor
For PWM dimming an input bipolar transistor with open collector output is recommended. This
will ensure the 200mV input shutdown threshold is achieved.
It is possible to PWM directly without a buffer transistor. This must be done with caution. Doing
this will overdrive the internal 1.25V reference. If a 2.5V input level is used at 100% PWM (DC) the
output current into the LED will be 2X the normal current which may destroy the ZXLD1350.
Overdriving with a 5V logic signal is very likely to damage the device as it exceeds the ADJ pin
voltage rating.
Soft start and decoupling capacitors
Any extra capacitor on the ADJ pin will affect the leading and falling edge of the PWM signal. Take
this into account as the rise time will be increased by approximately 0.5ms/nF.
Compare this with a 100Hz PWM. 50% duty cycle T
on
and T
off
are 5ms at 1% duty cycle T
on
is
0.1ms. 1nF on the ADJ pin will cause 0.5ms rise time which result in an error and limitation in
dimming at low duty cycles.
© Zetex Semiconductors plc 2006
ZETEX [ ZETEX SEMICONDUCTORS ]
