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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
Description  
The ZL50022 is a maximum 4,096 x 4,096 channel non-blocking digital Time Division Multiplex (TDM) switch. It has  
thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and  
Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be  
independently programmed to operate at any of the following data rates: 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or  
16.384 Mbps. The ZL50022 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the  
use of external tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be  
configured to operate in bi-directional mode, in which case STi0 - 31 will be ignored.  
The device contains two types of internal memory - data memory and connection memory. There are four modes of  
operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the  
contents of the connection memory define, for each output stream and channel, the source stream and channel  
(the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for  
the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be  
broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and  
status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with  
a pseudo-random bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the  
input side channels can be routed to one of 32-bit error detectors. In high impedance mode the selected output  
channel can be put into a high impedance state.  
When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external  
20.000 MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input  
reference signals (which can be 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz  
provided on REF0 - 3). The on-chip DPLL operates in normal, holdover or freerun mode and offers jitter  
attenuation. The jitter attenuation function exceeds the Stratum 4E specification.  
The configurable non-multiplexed microprocessor port allows users to program various device operating modes  
and switching configurations. Users can employ the microprocessor port to perform register read/write, connection  
memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or  
Intel-type microprocessors.  
The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.  
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Zarlink Semiconductor Inc.