ZL38001
Data Sheet
Pin Description
QSOP
Pin #
TQFP
Pin #
Name
Description
1
43
ENA1
SSI Enable Strobe/ST-BUS & GCI Mode for Rin/Sout (Input). This pin
has dual functions depending on whether SSI or ST-BUS/GCI is selected.
For SSI, this strobe must be present for frame synchronization. This is an
active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for on Rin/Sout pins. Strobe period is 125
microseconds. For ST-BUS or GCI, this pin, in conjunction with the MD1
pin, selects the proper mode for Rin/Sout pins (see ST-BUS and GCI
Operation description).
2
3
45
46
MD1
ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI
operation, this pin, in conjunction with the ENA1 pin, will select the proper
mode for Rin/Sout pins (see ST-BUS and GCI Operation description).
Connect this pin to Vss in SSI mode.
ENA2
SSI Enable Strobe /ST-BUS & GCI Mode for Sin/Rout (Input). This pin
has dual functions depending on whether SSI or ST-BUS/GCI is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide,
enabling serial PCM data transfer on Sin/Rout pins. Strobe period is 125
microseconds. For ST-BUS/GCI, this pin, in conjunction with the MD2 pin,
selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation
description).
4
5
6
47
48
2
MD2
Rin
Sin
IC
ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI
operation, this pin in conjunction with the ENA2 pin, selects the proper
mode for Sin/Rout pins (see ST-BUS and GCI Operation description).
Connect this pin to Vss in SSI mode.
Receive PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM
input stream. Data may be in either companded or 2’s complement linear
format. This is the Receive Input channel from the line (or network) side.
Data bits are clocked in following SSI, GCI or ST-BUS timing requirements.
Send PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input
stream. Data may be in either companded or 2’s complement linear format.
This is the Send Input channel (from the microphone). Data bits are
clocked in following SSI, GCI or ST-BUS timing requirements.
7
8
3
5
Internal Connection (Input). Must be tied to Vss.
MCLK Master Clock (Input). Nominal 20 MHz Master Clock input (may be
asynchronous relative to 8 KHz frame signal.) Tie together with MCLK2
(pin 33).
9,10,11
12
6, 7, 8
9
IC
Internal Connection (Input). Must be tied to Vss.
LAW
A/µ Law Select (Input). When low, selects µ−Law companded PCM.
When high, selects A-Law companded PCM. This control is for both serial
pcm ports.
13
14
11
13
FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code.
When high, selects ITU-T (G.711) PCM code. This control is for both serial
pcm ports.
RESET Reset / Power-down (Input). An active low resets the device and puts the
ZL38001 into a low-power stand-by mode.
3
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
