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ZL30402/QCC 参数 Datasheet PDF下载

ZL30402/QCC图片预览
型号: ZL30402/QCC
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH网元PLL [SONET/SDH Network Element PLL]
分类和应用: 电信集成电路异步传输模式ATM
文件页数/大小: 44 页 / 471 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL30402  
Data Sheet  
AC Electrical Characteristics - Input to Output Phase Alignment (after RefAlign change from 1 to 0)*  
Characteristics  
Symbol  
Min.  
Max.  
Units  
Notes  
1
2
8 kHz ref pulse width high  
tR8H  
tR8D  
100  
-15  
100  
210  
100  
192  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
F8o to 8 kHz ref input delay  
115  
220  
202  
Note 1  
3
1.544 MHz ref pulse width high  
1.544 MHz ref input to F8o delay  
2.048 MHz ref pulse width high  
2.048 MHz ref input to F8o delay  
19.44 MHz ref pulse width high  
F8o to 19.44 MHz ref input delay  
19.44 MHz ref input to C19o delay  
Reference input rise and fall time  
tR1.5H  
tR1.5D  
tR2H  
4
5
6
tR2D  
7
tR19H  
tR19D  
tR19C19D  
tIR, tIF  
8
5
14  
4
9
-4  
10  
10  
* Supply voltage and operating temperature are as per Recommended Operating Conditions  
Note 1: For 8 kHz reference alignment refer to Application Note ZL-27 "Phase Alignment between 8 kHz Output and 8 kHz Input Reference on  
ZL30402"  
t
R8H  
t
R8D  
PRI/SEC  
8 kHz  
VT  
t
R1.5H  
tc = 125 s  
µ
t
R1.5D  
PRI/SEC  
VT  
VT  
1.544 MHz  
t
R2H  
tc = 647.67 ns  
tc = 488.28 ns  
t
R2D  
PRI/SEC  
2.048 MHz  
t
R19D  
t
R19H  
PRI/SEC  
VT  
VT  
19.44 MHz  
tc = 51.44 ns  
tc = 51.44 ns  
t
R19C19D  
C19o  
F8o  
VT  
tc = 125 s  
µ
Note: Delay time measurements are done with jitter free input reference signals  
Figure 16 - Input Reference to Output Clock Phase Alignment  
38  
Zarlink Semiconductor Inc.  
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