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ZL30110LDE1 参数 Datasheet PDF下载

ZL30110LDE1图片预览
型号: ZL30110LDE1
PDF下载: 下载PDF文件 查看货源
内容描述: 电信速率转换DPLL [Telecom Rate Conversion DPLL]
分类和应用: 电信集成电路电信电路
文件页数/大小: 21 页 / 293 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL30110  
Data Sheet  
1.2 Pin Description  
Pin # Name  
Input Reference  
I/O  
Type  
Description  
28  
REF  
I
Reference (LVCMOS, Schmitt Trigger). This is the input reference source  
used for synchronization. One of four possible frequencies may be used: 8 kHz,  
2.048 MHz, 8.192 MHz or 16.384 MHz. This pin is internally pulled down to  
GND.  
Master Clock  
11  
OSCi  
I
Oscillator Master Clock (Input). For crystal operation, a 25 MHz crystal is  
connected from this pin to OSCo. For clock oscillator operation, this pin must be  
connected to a clock source.  
10  
OSCo  
O
Oscillator Master Clock (LVCMOS). For crystal operation, a 25 MHz crystal is  
connected from this pin to OSCi. This output is not suitable for driving other  
devices (see C25o output pin for support of such function). For clock oscillator  
operation, this pin must be left unconnected.  
Control and Status  
9
RST  
I
I
Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device.  
On power up, the RST pin must be held low for a minimum of 300 ns after the  
power supply pins have reached the minimum supply voltage. When the RST  
pin goes high, the device will transition into a Reset state for 3 ms. In the  
Reset state all outputs will be forced into high impedance.  
13  
OUT_SEL  
Output Select (LVCMOS, Schmitt Trigger). This input pin selects the output  
clock frequency of the C100/66o, a logic low selects the 100 MHz output,  
while logic high selects the 66 MHz output clock.  
3
2
REF_FAIL  
LOCK  
O
O
Reference Failure Indicator (LVCMOS). A logic high at this pin indicates that  
the REF reference frequency is exhibiting abrupt phase or frequency change.  
Lock Indicator (LVCMOS). This output goes to a logic high when the PLL is  
frequency locked to a valid input reference.  
Output Clocks  
19  
26  
25  
24  
23  
C65o  
O
O
O
O
O
Clock 65.536 MHz (LVCMOS). This output is used in general TDM applications.  
The falling edge of this clock is aligned with rising edge of the input reference  
(REF).  
C25ao  
C25bo  
C25co  
C25do  
Clock 25 MHz (LVCMOS). This is a buffered external oscillator clock, the phase  
and frequency accuracy of this output tracks that of the external crystal or  
oscillator.  
Clock 25 MHz (LVCMOS). This is a buffered external oscillator clock, the phase  
and frequency accuracy of this output tracks that of the external crystal or  
oscillator.  
Clock 25 MHz (LVCMOS). This is a buffered external oscillator clock, the phase  
and frequency accuracy of this output tracks that of the external crystal or  
oscillator.  
Clock 25 MHz (LVCMOS). This is a buffered external oscillator clock, the phase  
and frequency accuracy of this output tracks that of the external crystal or  
oscillator.  
6
Zarlink Semiconductor Inc.