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ZL30110LDE1 参数 Datasheet PDF下载

ZL30110LDE1图片预览
型号: ZL30110LDE1
PDF下载: 下载PDF文件 查看货源
内容描述: 电信速率转换DPLL [Telecom Rate Conversion DPLL]
分类和应用: 电信集成电路电信电路
文件页数/大小: 21 页 / 293 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL30110  
Data Sheet  
AC Electrical Characteristics* - Timing for input reference (see Figure 8).  
Characteristics  
8 kHz reference period  
Symbol  
Min.  
Typ.  
Max.  
Units  
1
2
3
4
5
tREF8kP  
tREF2P  
tREF8P  
tREF16P  
tREFW  
120  
263  
63  
125  
488  
122  
61  
128  
712  
175  
75  
µs  
ns  
ns  
ns  
ns  
2.048 MHz reference period  
8.192 MHz reference period  
16.384 MHz reference period  
reference pulse width high or low  
38  
15  
* Supply voltage and operating temperature are as per Recommended Operating Conditions.  
* Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within  
+/-130 ppm limit.  
AC Electrical Characteristics* - Input to output timing for synchronous clock (see Figure 8).  
Characteristics  
Symbol  
Min.  
Max.  
Units  
1
2
3
4
5
6
8 kHz reference input to C65o delay  
2.048 MHz reference input to C65o delay  
8.192 MHz reference input to C65o delay  
16.384 MHz reference input to C65o delay  
C65o pulse width low  
tREF8_C65D  
tREF2_C65D  
tREF8_C65D  
tREF16_C65D  
tC65L  
-0.7  
1.5  
2.1  
2.1  
7.0  
1.1  
6.7  
9.6  
9.2  
9.6  
8.6  
2.3  
ns  
ns  
ns  
ns  
ns  
ns  
Output clock rise or fall time  
tORF  
* Supply voltage and operating temperature are as per Recommended Operating Conditions.  
Outputs loaded with 30 pF.  
t
REF<xx>P  
t
t
REFW  
REFW  
REF  
t
REF<x>_C65D  
t
C65L  
C65o  
Figure 8 - Input to Output Timing for Synchronous Clock  
17  
Zarlink Semiconductor Inc.  
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