ZL30110
Data Sheet
5.0 Applications
This section contains ZL30110 application specific details for power supply decoupling, reset operation, clock and
crystal operation.
5.1 Power Supply Decoupling
Jitter levels on the ZL30110 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30110 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
5.2 Master Clock
The ZL30110 can use either a clock or crystal as the master timing source.
5.2.1 Clock Oscillator
When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency,
frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30110, and the OSCo
output should be left open as shown in Figure 5.
1
2
3
4
Frequency
Tolerance
Rise & fall time
Duty cycle
25 MHz
as required (better than +/-50ppm)
< 8 ns
40% to 60%
Table 1 - Clock Oscillator Specification
ZL30110
+3.3 V
OSCi
+3.3 V
25 MHz OUT
GND
0.1 µF
OSCo
No Connection
Figure 5 - Clock Oscillator Circuit
12
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
