MT90826
Data Sheet
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
Characteristics
CS setup from DS falling
Sym. Min. Typ. Max. Units Test Conditions
1
2
3
4
5
6
7
8
tCSS
tRWS
tADS
tCSH
tRWH
tADH
tDDR
tDHR
0
10
2
ns
ns
ns
ns
ns
ns
ns
ns
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
0
R/W hold after DS rising
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
2
10
27
12
CL=150pF
20
CL=150pF, RL=1K
Note 1
9
Data setup on write (register write2)
tDSW
tSWD
0
ns
10 Valid Data Delay on write (memory write3)
For 16 Mbps, 16&8 Mbps, 8 Mbps, 4&8 Mbps
modes
50
85
ns
ns
ns
For 4 Mbps, 4&2 Mbps modes
For 2 Mbps mode
185
11 Data hold on write
tDHW
tAKD
13
ns
ns
12a Acknowledgment Delay: Register RD or WR
55
CL=150pF
CL=150pF
12b Acknowledgment Delay: Memory RD or WR
For 16 Mbps, 16&8 Mbps, 8 Mbps, 4&8 Mbps
modes
tAKD
100
140
240
ns
ns
ns
For 4 Mbps, 4&2 Mbps modes
For 2 Mbps mode
13 Acknowledgment Hold Time
tAKH
24
ns
CL=150pF, RL=1K,
Note 1
Note:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
2. Register write timing refers to the rising edge of DS at the end of the write cycle.
3. Memory write timing refers to the falling edge of DS at the beginning of the write cycle.
41
Zarlink Semiconductor Inc.
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