MT88E41
Data Sheet
Office. The received data can be processed externally by a microcontroller, stored in memory, or displayed as
is, depending on the application.
IN+
IN-
GS
VRef
CAP
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
IC2
IC1
PWDN
CD
DR
DATA
DCLK
16 PIN PLASTIC DIP/SOIC
IN+
IN-
GS
VRef
CAP
NC
OSC1
NC
OSC2
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
IC2
NC
NC
IC1
PWDN
CD
DR
DATA
DCLK
20 PIN SSOP
Figure 2 - Pin Connections
Pin Description Table
Pin
#
Name
16
1
2
3
4
5
6
7
8
9
20
1
2
3
4
5
7
9
10
11
IN+
IN-
GS
V
Ref
Non-inverting Op-Amp (Input).
Inverting Op-Amp (Input).
Gain Select (Output).
Gives access to op-amp output for connection of feedback
resistor.
Voltage Reference (Output).
Nominally V
DD/2
. This is used to bias the op-amp
inputs.
Description
CAP
Capacitor.
Connect a 0.1µF capacitor to V
SS
.
OSC1
Oscillator (Input).
Crystal connection. This pin can be driven directly from an
external clocking source.
OSC2
Oscillator (Output).
Crystal connection. When OSC1 is driven by an external
clock, this pin should be left open.
V
SS
Power supply ground.
DCLK
Data Clock (Output).
Outputs a clock burst of 8 low going pulses at 1202.8Hz
(3.5795MHz divided by 2976). Every clock burst is initiated by the DATA stop bit
start bit sequence. When the input DATA is 1202.8 baud, the positive edge of each
DCLK pulse coincides with the middle of the data bits output at the DATA pin. No
DCLK pulses are generated during the start or stop bits. Typically, DCLK is used to
clock the eight data bits from the 10 bit data word into a serial-to-parallel converter.
DATA
Data (Output).
Serial data output corresponding to the FSK input and switching at
the input baud rate. Mark frequency at the input corresponds to a logic high, while
space frequency corresponds to a logic low at the DATA output. With no FSK
input, DATA is at logic high. This output stays high until CD has become active.
DR
Data Ready (Open Drain Output).
This output goes low after the last DCLK pulse
of each word. This can be used to identify the data (8-bit word) boundary on the
serial output stream. Typically, DR is used to latch the eight data bits from the
serial-to-parallel converter into a microcontroller.
Carrier Detect (Open Drain Output).
A logic low indicates that a carrier has been
present for a specified time on the line. A time hysteresis is provided to allow for
momentary discontinuity of carrier.
10
12
11
13
12
14
CD
2
SEMICMF.019
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
