MT88E39
Data Sheet
word N+1
word N
7
Demodulated
Data
(Internal Signal)
stop
0
2
3
4
6
7
stop
start
1
5
tRL
DR (Data Ready)
¿
¡
1/fDCLK1
CMOS
tDDS
Output
tDDH
DCLK (Data Clock)*
Schmitt Input
DATA Output
0
6
7
0
1
2
3
4
5
6
7
word N
word N-1
*
The DCLK input must be low before and after DR falling edge
DCLK clears DR
¿
¡ DCLK does not clear DR, so DR is low for maximum time (1/2 bit time)
Figure 12 - Serial Data Interface Timing (Mode 1)
14
Zarlink Semiconductor Inc.