MT8889C
which employs a burst counter to synthesize precise
tone bursts and pauses. A call progress mode can
be selected so that frequencies within the specified
passband can be detected. The adaptive micro
interface allows microcontrollers, such as the
68HC11, 80C51 and TMS370C50, to access the
MT8889C internal registers.
C1
R1
IN+
IN-
C2
R4
R5
GS
Input Configuration
The input arrangement of the MT8889C provides a
differential-input operational amplifier as well as a
bias source (V
Ref
), which is used to bias the inputs at
V
DD
/2. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for gain
adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.
Figure 4 shows the necessary connections for a
differential input configuration.
R3
R2
V
Ref
MT8889C
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(A
V
diff) - R5/R1
INPUT IMPEDANCE
(Z
IN
diff) = 2 R1
2
+ (1/ωC)
2
Receiver Section
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). The filters
also incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at the
frequencies of the incoming DTMF signals.
IN+
Figure 4 - Differential Input Configuration
F
LOW
F
HIGH
DIGIT
D
3
D
2
D
1
D
0
697
697
697
770
770
770
852
852
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
C
R
IN
IN-
R
F
GS
852
941
V
Ref
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
MT8889C
941
941
697
770
852
941
Figure 3 - Single-Ended Input Configuration
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table
3
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
