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MT8889CP 参数 Datasheet PDF下载

MT8889CP图片预览
型号: MT8889CP
PDF下载: 下载PDF文件 查看货源
内容描述: [DTMF Signaling Circuit, CMOS, PQCC28, PLASTIC, LCC-28]
分类和应用: 电信电信集成电路
文件页数/大小: 29 页 / 488 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT8889C
Integrated DTMF Transceiver
with Adaptive Micro Interface
Data Sheet
Features
Central office quality DTMF transmitter/receiver
Low power consumption
High speed adaptive micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30dBm
July 2003
Ordering Information
MT8889CE
20 Pin Plastic DIP
MT8889CS
20 Pin SOIC
MT8889CN
24 Pin SSOP
MT8889CP
28 Pin Plastic LCC
-40°C to +85°C
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT8889C utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external logic.
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Description
The MT8889C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
Functional Description
The MT8889C Integrated DTMF Transceiver consists
of a high performance DTMF receiver with an internal
gain setting amplifier and a DTMF generator, which
TONE
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
V
DD
V
Ref
V
SS
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
DS/RD
CS
R/W/WR
RS0
Steering
Logic
Receive Data
Register
ESt
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.