Preliminary Information MT8885
Bit
Name
Status Flag Set
Status Flag Cleared
b0
IRQ
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Interrupt is inactive. Cleared after
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2
b3
RECEIVE DATA REGISTER
FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
DELAYED STEERING
Set upon the valid detection of the Cleared upon the detection of a
absence of a DTMF signal. valid DTMF signal.
Table 8. Status Register Description
V
DD
MT8885
C3
VDD
St/GT
ESt
D3
IN+
C1
R1
C2
DTMF/CP
INPUT
IN-
R4
GS
R3
R2
VRef
VSS
OSC1
D2
X-tal
D1
D0
OSC2
NC
NC
PWDN
IRQ/CP
To µP
or µC
NC
C4
DTMF
OUTPUT
TONE
R/W/WR
CS
DS/RD
RS0
R
LT
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 kΩ 1%
R4 = 3.3 kΩ 10%
* Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT8885 can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
R
= 10 kΩ (min.) 50 kΩ (max.)
LT
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
C4 = 0.1µf
X-tal = 3.579545 MHz
Figure 13 - Application Circuit (Single-Ended Input)
4-61
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
