MT8885
7.0
DTMF Clock Circuit
Data Sheet
The internal clock circuit is completed with the additions of a standard television colour burst crystal. The crystal
specification is as follows:
Frequency:
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Maximum Series Resistance:
Maximum Drive Level:
3.579545 MHz
±0.1%
Parallel
18 pF
150 ohms
2 mW
e.g.CTS Knights MP036S
Toyocom TQC-203-A-9S
A number of MT8885 devices can be connected as shown in Figure 11 such that only one crystal is required.
Alternatively, the OSC1 inputs on all devices can be driven from a CMOS buffer with the OSC2 outputs left
unconnected.
MT8885
OSC1 OSC2
MT8885
OSC1 OSC2
MT8885
OSC1 OSC2
3.579545 MHz
Figure 11 - Common Crystal Connection
8.0
Microprocessor Interface
The MT8885 design incorporates an adaptive interface, which allows it to be connected to various kinds of
microprocessors. Key functions of this interface include the following:
•
•
Continuous activity on DS/RD is not necessary to update the internal status registers.
Compatible with Motorola and Intel processors. Determines whether input timing is that of an Intel or
Motorola controller by monitoring
DS/RD, on the CS falling edge.
Differentiates between multiplexed and non-multiplexed microprocessor buses. Address and data are
latched in accordingly.
•
Figure 16 shows the timing diagram for the Motorola microcontrollers. The chip select (CS) input is formed by
NANDing address strobe (AS) and address decode output. The MT8885 examines the state of DS/RD on the falling
edge of CS. For Motorola bus timing DS/RD must be low on the falling edge of CS. Figure 12(a) shows the
connection of the MC68HC11 Motorola processor to the MT8885 DTMF transceiver.
Figures 17 and 18 are the timing diagrams for Intel micro-controllers with multiplexed address and data buses. The
MT8885 latches in the state of DS/RD on the falling edge of CS. When DS/RD is high, Intel processor operation is
selected. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS
can be generated. Figure 12(b) shows the connection of these Intel processors to the MT8885 transceiver.
12
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
