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MT8870DE1-1 参数 Datasheet PDF下载

MT8870DE1-1图片预览
型号: MT8870DE1-1
PDF下载: 下载PDF文件 查看货源
内容描述: [DTMF Signaling Circuit, CMOS, PDIP18, LEAD FREE, PLASTIC, MS-001AC, DIP-18]
分类和应用: 光电二极管
文件页数/大小: 19 页 / 424 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT8870D/MT8870D-1
ISO
2
-CMOS
Integrated DTMF Receiver
Data Sheet
Features
Complete DTMF Receiver
Low power consumption
Internal gain setting amplifier
Adjustable guard time
Central office quality
Power-down mode
Inhibit mode
Backward compatible with MT8870C/MT8870C-1
MT8870DE
MT8870DS
MT8870DN
MT8870DSR
MT8870DNR
MT8870DN1
MT8870DE1
MT8870DS1
MT8870DNR1
MT8870DSR1
MT8870DE1-1
MT8870DS1-1
MT8870DSR1-1
October 2006
Ordering Information
18 Pin PDIP
18 Pin SOIC
20 Pin SSOP
18 Pin SOIC
20 Pin SSOP
20 Pin SSOP*
18 Pin PDIP*
18 Pin SOIC*
20 Pin SSOP*
18 Pin SOIC*
18 Pin PDIP*
18 Pin SOIC*
18 Pin SOIC*
*Pb Free Matte Tin
Tubes
Tubes
Tubes
Tape &
Tape &
Tubes
Tubes
Tubes
Tape &
Tape &
Tubes
Tubes
Tape &
Reel
Reel
Reel
Reel
Reel
Applications
Receiver system for British Telecom (BT) or
CEPT Spec (MT8870D-1)
Paging systems
Repeater systems/mobile radio
Credit card systems
Remote control
Personal computers
Telephone answering machine
VDD
VSS
VRef
INH
-40°C to +85°C
Description
The MT8870D/MT8870D-1 is a complete DTMF
receiver integrating both the bandsplit filter and digital
decoder functions. The filter section uses switched
capacitor techniques for high and low group filters;
the decoder uses digital counting techniques to detect
and decode all 16 DTMF tone-pairs into a 4-bit code.
PWDN
Bias
Circuit
VRef
Buffer
Q1
High Group
Filter
Dial
Tone
Filter
Low Group
Filter
Zero Crossing
Detectors
Digital
Detection
Algorithm
Code
Converter
and Latch
Q2
Q3
Q4
Chip Chip
Power Bias
IN +
IN -
GS
to all
Chip
Clocks
St
GT
Steering
Logic
OSC1
OSC2
St/GT
ESt
STD
TOE
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2006, Zarlink Semiconductor Inc. All Rights Reserved.