MT8870D/MT8870D-1
Data Sheet
AC Electrical Characteristics - VDD=5.0V±5%, VSS=0V, -40°C ≤ To ≤ +85°C, using Test Circuit shown in Figure 10.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Conditions
1
2
Tone present detect time
Tone absent detect time
Tone duration accept
tDP
tDA
5
11
4
14
8.5
40
ms
ms
ms
ms
ms
ms
µs
Note 1
0.5
Note 1
T
I
3
tREC
tREC
tID
Note 2
M
I
4
Tone duration reject
20
20
Note 2
N
G
5
Interdigit pause accept
Interdigit pause reject
40
Note 2
6
tDO
Note 2
7
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data set up (Q to StD)
tPQ
8
11
16
TOE=VDD
TOE=VDD
TOE=VDD
8
O
U
T
tPStD
tQStD
tPTE
12
3.4
50
µs
9
µs
P
U
T
10
Propagation delay (TOE to Q
ENABLE)
ns
load of 10 kΩ,
50 pF
S
11
Propagation delay (TOE to Q
DISABLE)
tPTD
300
ns
load of 10 kΩ,
50 pF
P
D
W
N
12
13
Power-up time
tPU
tPD
30
20
ms
ms
Note 3
Power-down time
14
Crystal/clock frequency
fC
3.575
9
3.579
5
3.583
1
MHz
C
L
O
C
K
15
16
17
18
Clock input rise time
Clock input fall time
Clock input duty cycle
Capacitive load (OSC2)
tLHCL
tHLCL
DCCL
CLO
110
110
60
ns
ns
%
Ext. clock
Ext. clock
Ext. clock
40
50
30
pF
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1.
2.
Used for guard-time calculation purposes only.
These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.
3.
With valid tone present at input, tPU equals time from PDWN going low until ESt going high.
14
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
