MT8841
AC Electrical Characteristics
†
- Timing
Characteristics
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DR
DCLK
DR
DCLK
DATA
DCLK
DATA
CD
PWDN
OSC1
Sym
t
PU
t
PD
t
IAL
t
IAH
Min
Typ
‡
35
100
Max
50
1000
25
Units
ms
µs
ms
ms
ms
11
Notes*
Power-up time
Power-down time
Input FSK to CD low delay
Input FSK to CD high delay
Hysteresis
Rate
Input FSK to DATA delay
Rise time
Fall time
DATA to DCLK delay
DCLK to DATA delay
Frequency
High time
Low time
DCLK to DR delay
Rise time
Fall time
Low time
8
8
1188
1200
1
1212
5
200
200
6
6
1200
416
416
1202.8
416
416
416
1205
417
417
417
10
200
415
416
417
bps
ms
ns
ns
µs
µs
Hz
µs
µs
µs
µs
ns
µs
6,12
t
IDD
t
R
t
F
t
DCD
t
CDD
t
CH
t
CL
t
CRD
t
RR
t
FF
t
RL
8
8
6, 7, 10
6, 7, 10
7
7
7
7
9
9
7
415
415
415
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25
°
C and are for design aid only, not guaranteed and not subject to production testing.
*Notes:
1.
dBm=decibels above or below a reference power of 1mW into 600Ω.
2.
Using unity gain test circuit shown in Figure 6.
3.
Mark and Space frequencies have the same amplitude.
4.
Band limited random noise (200-3200Hz).
5.
Referenced to the minimum input detection level.
6.
FSK input data at 1200
±
12 baud.
7.
OSC1 at 3.579545 MHz
±
0.2%.
8.
10k to V
SS
, 50pF to V
SS.
9.
10k to V
DD
, 50pF to V
SS
.
10.
Function of signal condition.
11.
The device will stop functioning within this time, but more time may be required to reach I
DDQ
.
12.
For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations.
t
CDD
t
DCD
t
R
DATA
t
F
t
FF
t
RR
DR
DCLK
t
RL
t
CL
t
R
t
CH
t
F
Figure 7 - DATA and DCLK Output Timing
Figure 8 - DR Output Timing
5-18
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
