MT8814
AC Electrical Characteristics
†
- Control and I/O Timings
- Voltages are with respect to V
DD
=5V, V
SS
=0V,
V
EE
=-7V, unless otherwise stated.
Data Sheet
Characteristics
1
Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
Digital Input Capacitance
Switching Frequency
Setup Time DATA to STROBE
Hold Time DATA to STROBE
Setup Time Address to STROBE
Hold Time Address to STROBE
Setup Time CS to STROBE
Hold Time CS to STROBE
STROBE Pulse Width
RESET Pulse Width
STROBE to Switch Status Delay
DATA to Switch Status Delay
RESET to Switch Status Delay
Sym.
CX
talk
Min.
Typ.
‡
30
Max.
Units
mVpp
Test Conditions
V
IN
=3V square wave;
R
IN
=1k, R
L
=10k.
See Appendix, Fig. A.6
f=1MHz
R
L
= 1k,
R
L
= 1k,
R
L
= 1k,
R
L
= 1k,
R
L
= 1k,
R
L
= 1k,
R
L
= 1k,
R
L
= 1k,
R
L
= 1k,
R
L
= 1k,
R
L
= 1k,
C
L
=50pF
1
C
L
=50pF
C
L
=50pF
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C
DI
F
O
t
DS
t
DH
t
AS
t
AH
t
CSS
t
CSH
t
SPW
t
RPW
t
S
t
D
t
R
10
10
10
10
10
10
20
40
10
20
pF
MHz
ns
ns
ns
ns
ns
ns
ns
ns
C
L
=50pF
1
C
L
=50pF
1
C
L
=50pF
C
L
=50pF
C
L
=50pF
C
L
=50pF
C
L
=50pF
C
L
=50pF
1
1
1
1
1
1
40
50
35
100
100
100
ns
ns
ns
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
‡ Typical figures are at 25
C and are for design aid only; not guaranteed and not subject to production testing.
Note 1: Refer to Appendix, Fig. A.7 for test circuit.
t
CSS
50%
CS
t
CSH
50%
t
RPW
50%
50%
RESET
t
SPW
50%
t
AS
50%
50%
STROBE
ADDRESS
50%
50%
t
AH
DATA
50%
t
DS
ON
t
DH
50%
SWITCH*
OFF
t
D
t
S
t
R
t
R
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
6
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
