MT312 参数 Datasheet PDF下载

MT312

10

10.1

10.2

10.2.1

10.2.2

10.2.3

10.2.4

10.2.5

10.2.6

10.2.7

10.2.8

10.2.9

10.2.10

10.2.11

10.2.12

10.2.13

10.2.14

10.2.15

10.2.16

10.2.17

10.2.18

10.2.19

10.2.20

10.2.21

10.2.22

10.2.23

10.2.24

10.2.25

10.2.26

10.2.27

10.2.28

10.2.29

10.2.30

10.2.31

10.2.32

10.2.33

10.2.34

10.2.35

10.2.36

10.2.37

10.2.38

10.2.39

10.2.40

10.2.41

10.2.42

10.2.43

10.2.44

10.2.45

10.2.46

10.2.47

10.2.48

10.2.49

10.2.50

10.2.51

10.2.52

10.3

10.4

10.4.1

6

Contents

Secondary Registers for Test and De-Bugging .................................................. 61

Read / Write Secondary Register Map ............................................................................................... 61

Secondary Registers for Test and De-Bugging Read/Write Registers .............................................. 63

AGC Initial Value. Register 40 (R/W) ......................................................................................... 63

AGC Maximum Value. Register 42 (R/W) .................................................................................. 63

AGC Minimum Value. Register 43 (R/W) ................................................................................... 63

AGC Lock Threshold Value. Register 44 (R/W) ......................................................................... 63

AGC Lock Threshold Value. Register 45 (R/W) ......................................................................... 63

AGC Power Setting Initial Value. Register 46 (R/W) .................................................................. 63

QPSK Miscellaneous. Register 47 (R/W) ................................................................................... 63

SNR Low Threshold Value. Register 48 (R/W) .......................................................................... 64

SNR HIGH Threshold Value. Register 49 (R/W) ........................................................................ 64

Timing Synchronisation Sweep Rate. Register 50 (R/W) ........................................................... 64

Timing Synchronisation Sweep Limit Low. Register 51 (R/W) ................................................... 64

Timing Synchronisation Sweep Limit High. Register 52 (R/W) .................................................. 64

Carrier Synchronisation Sweep Rate 1. Register 53 (R/W) ........................................................ 64

Carrier Synchronisation Sweep Rate 2. Register 54 (R/W) ........................................................ 64

Carrier Synchronisation Sweep Rate 3. Register 55 (R/W) ........................................................ 65

Carrier Synchronisation Sweep Rate 4. Register 56 (R/W) ........................................................ 65

Carrier Synchronisation Sweep Limit. Register 57 (R/W) ........................................................... 65

Timing Synchronisation Coefficients. Registers 58 - 60 (R/W) ................................................... 65

Carrier Synchronisation Proportional Part Coefficients. Registers 61 - 62 (R/W) ...................... 65

Carrier Synchronisation Integral Coefficients. Registers 63 - 64 (R/W) ..................................... 66

QPSK Output Scale Factor. Register 65 (R/W) .......................................................................... 66

Timing Lock Detect Threshold out of lock. Register 66 (R/W) .................................................... 66

Timing Lock Detect Threshold in lock. Register 67 (R/W) .......................................................... 66

Frequency Lock Detect Threshold. Register 68 ......................................................................... 66

Phase Lock Detect Threshold out of lock. Registers 69 - 72 (R/W) ........................................... 67

Phase Lock Detect Threshold in lock. Registers 73 - 76 (R/W) ................................................. 67

Phase Lock Detect Accumulator Time. Register 77 (R/W) ......................................................... 67

Sweep PAR. Register 78 (R/W) ................................................................................................. 68

Start up Time. Register 79 (R/W) ............................................................................................... 68

Loss Lock Threshold. Register 80 (R/W) .................................................................................... 68

FEC Lock Time. Register 81 (R/W) ............................................................................................ 68

Loss Lock Time. Register 82 (R/W) ............................................................................................ 69

Viterbi Error Period. Registers 83 - 85 (R/W) ............................................................................. 69

Viterbi Set up. Register 86 (R/W) ............................................................................................... 69

Viterbi Reference Byte 0. Register 87 (R/W) .............................................................................. 70

Viterbi Reference Byte 1. Register 88 (R/W) .............................................................................. 70

Viterbi Reference Byte 2. Register 89 (R/W) .............................................................................. 70

Viterbi Reference Byte 3. Register 90 (R/W) .............................................................................. 70

Viterbi Reference Byte 4. Register 91 (R/W) .............................................................................. 70

Viterbi Reference Byte 5. Register 92 (R/W) .............................................................................. 70

Viterbi Reference Byte 6. Register 93 (R/W) .............................................................................. 70

Viterbi Maximum Error. Register 94 (R/W) ................................................................................. 70

Byte Align Set up. Register 95 (R/W) ......................................................................................... 71

Program Synchronising Byte. Register 98 (R/W) ....................................................................... 71

AFC Frequency Search Threshold. Register 99 (R/W) .............................................................. 71

Accumulator Differential Threshold. Register 100 (R/W) ............................................................ 71

QPSK Lock Control. Register 101 (R/W) ................................................................................... 71

QPSK State Control. Register 102 (R/W) .................................................................................. 72

QPSK Reset. Register 104 (R/W) .............................................................................................. 72

QPSK Test Control. Register 105 (R/W) .................................................................................... 72

QPSK Test State. Register 106 (R/W) ....................................................................................... 73

Test Mode. Register 125 (R/W) .................................................................................................. 73

Read only Secondary Register Map .................................................................................................. 73

Secondary Registers for Test and De-Bugging Read Register .......................................................... 73

Test Read. Register 107 (R) ....................................................................................................... 73