Design Manual MT312
The MT312 provides a monitor of Bit Error Rate after
the QPSK module and also after the Viterbi module.
Quick start overview
The MT312 is a QPSK/BPSK 1 to 45MBaud
demodulator and channel decoder for digital satellite
television transmissions compliant to both DVB-S
and DSS standards and other systems, such as
LMDS, that use the same architecture.
For receiver installation, a high speed scan or 'blind
search' mode is available. This allows all signals
from a given satellite to be evaluated for frequency,
symbol rate and convolutional coding scheme. The
phase of the IQ signals can be automatically
determined.
A Command Driven Control (CDC) system is
provided making the MT312 very simple to program.
After the tuner has been programmed to the required
frequency, to acquire a DVB transmission, the
MT312 requires a minimum of five registers to be
written. Activity flow diagrams for initialisation and
basic channel change are included in section 2.
Full DiSEqC™ v2.2 is provided for both writing and
reading DiSEqC™ messages. Storage in registers
for up to eight data bytes sent and eight data bytes
received is provided.
MPEG/
DSS
Packets
I I/P
Timing recovery
Matched filter
Phase recovery
DVB
DSS
FEC
Decimation
Filteriing
Dual ADC
De-rotator
Q I/P
Bus I/O
Analog
AG
Ccontrol
Acquisition
Control
I?C
Interface
Clock Generation
Figure 3 - MT312 Functional Block Diagram
Additional Features
De-Interleaver
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•
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2-wire bus microprocessor interface.
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Compliant with DVB and DSS standards.
All digital clock and carrier recovery.
On-chip PLL clock generation using low cost 10
to 15MHz crystal.
Reed Solomon
•
(204, 188) for DVB and (146,130) for DSS.
•
•
•
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3.3V operation.
•
Reed Solomon Bit-error-rate monitor to indicate
Viterbi performance.
80 pin MQFP package.
Low external component count.
Commercial temperature range 0 to 70°C.
De-Scrambler
•
EBU specification De-scrambler for DVB mode.
Demodulator
•
BPSK or QPSK programmable.
Outputs
•
Optional fast acquisition mode for low symbol
rates.
•
MPEG transport parallel & serial output.
•
MPEG clock input for external synchronising of
MPEG data output.
Viterbi
•
Integrated MPEG2 TEI bit processing for DVB
only.
•
Programmable decoder rates 1/2, 2/3, 3/4, 5/6,
6/7, 7/8.
•
•
•
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Automatic spectrum resolution of IQ phase.
Constraint length k=7.
Application Support
•
•
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Channel decoder system evaluation board.
Windows based evaluation software.
ANSI C generic software.
Trace back depth 128.
Extensive SNR and BER monitors.
3
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