MT093
Pin Description
Pin #
PDIP
PLCC
Data Sheet
Name
20
Description
18
19
20
21
22, 23
24, 25
26, 27
28 - 33
34
35
36
37
38
39
40
21
22
23
24,25
26,27
28-31
32-37
38,39
40
-
41
42
43
44
STROBE
STROBE (Input):
enables function selected by address and data. Address must
be stable before STROBE goes high and DATA must be stable on the falling edge
of the STROBE. Active High.
Y5
Y5 Analog (Input/Output):
this is connected to the Y5 column of the switch
array.
Ground Reference.
V
SS
Y4
Y4 Analog (Input/Output):
this is connected to the Y4 column of the switch
array.
AX1,AX2
X1 and X2 Address Lines (Inputs).
AY0,AY1
Y0 and Y1 Address Lines (Inputs).
NC
No Connection.
X5-X0
X5-X0 Analog (Inputs/Outputs):
these are connected to the X5-X0 rows of the
switch array.
NC
No Connection.
Y0
Y0 Analog (Input/Output):
this is connected to the Y0 column of the switch array.
NC
No Connection.
Y1
Y1 Analog (Input/Output):
this is connected to the Y1 column of the switch array.
DATA
DATA (Input):
a logic high input will turn on the selected switch and a logic low will
turn off the selected switch. Active High.
Y2
Y2 Analog (Input/Output):
this is connected to the Y2 column of the switch array.
V
DD
Positive Power Supply.
Functional Description
The MT093 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there are
8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X input/output
lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on and provide a
high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits
are selected by the address input lines (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input
line. Data is asynchronously written into memory whenever the STROBE input is high and is latched on the falling
edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical
“0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are
altered when data is written into memory. The remaining switches retain their previous states. Any combination of X
and Y lines can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the
RESET input line will asynchronously return all memory locations to logical “0” turning off all crosspoint switches.
Address Decode
The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the
resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a
location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and
then low causing the data to be latched. The data can be changed while STROBE is high, however, the
corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of
STROBE in order for correct data to be written to the latch.
3
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
