Preliminary Information
Value
Characteristics
Min.
1900MHz RF output stage (PCS)
Typ.
Max.
Units
MGCT04
Conditions
Specifications assume 50 ohm
load driven via a matching network
(Fig. 5)
RF amplifier operating frequency
range
Output power
ACPR (CDMA)
ACPR (TDMA)
1850
+8
-66
-45
-90
1910
+18
-52
-30
-60
-128
-123
-121
MHz
dBm
dBc
dBc
dBc
dBm/
Hz
dBm/
Hz
Note 1
Pout = +3dBm Vcc = 3V
Pout = +8dBm, Offset = 30kHz
Vcc = 3V
Pout = +8dBm, Offset = 60kHz
Vcc = 3V
At duplex frequency, offset 80MHz
Pout = +3dBm
ftx = 1910MHz, Pout = +8dBm
Receive band noise
Receive band noise
(1930 - 1990 MHz)
Spurious Outputs
LO Leakage
Image Rejection
Other Spurii
-30
-30
-20
-20
-20
dBc
dBc
dBm
Pout = +8dBm
Pout = +8dBm
Note 3
Table 3 - AC Characteristics (continued)
Notes:
1. V (I/Q) = 1.4V differential, VHF LO = 22mV rms, UHF LO = -15dBm, VGA = 2.6volts
2. V (I/Q) = 1.4 V dc differential, VHF LO = 22mV rms, UHF LO = -15dBm, VGA = 2.6 volts
3. Frequency range 10MHz to 10*ftx except Rx and Tx bands
Circuit Description
General
The MGCT04 circuit is designed to provide the
transmit function in dual band dual mode CDMA/
AMPS IS136/AMPS mobile phones. The circuit
contains the following blocks:
1. Quadrature modulator
2. VHF voltage controlled oscillator buffer and
divide by 8 prescaler
3. Active IF low pass filter
4. IF variable gain amplifier
5. Single sideband mixer with external UHF
oscillator inputs
6. RF variable gain amplifier
7. 900MHz and 1900MHz high power output driver
stages
8. Power and mode control logic
is applied to the I and Q inputs of the quadrature
modulator to produce the intermediate frequency by
mixing with the local oscillator frequency from the
VHF VCO. The control inputs can select either a
divide by two or divide by four function between the
VHF VCO and the quadrature modulator giving a
choice of possible intermediate frequencies.
VHF Oscillator Input Oscillator Bias and
Divider
An external VHF oscillator circuit is AC coupled to
the VHF oscillator input. The oscillator drives the
quadrature modulator and an internal divide by eight
circuit to reduce the frequency of the output signal to
be sent off chip to the frequency synthesiser. This
reduces the power required in the output buffer
circuit and also allows a low frequency low power
CMOS synthesiser to be used. The divider can be
disabled if not required by connecting the output pin
(DIV OUT - pin 7) to the positive power supply. This
reduces the total supply current by typically 4mA. An
oscillator bias circuit is included on the chip so that
the external VHF oscillator transistor can be switched
off using the control inputs. The bias voltage is
5
Quadrature Modulator
I and Q data from a baseband circuit such as the
Zarlink Semiconductor MGCM02 or MGCM03 circuit
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
