Data Sheet
MGCM02
The synthesisers include 2 modulus prescalers
programmable from 8/9 to 128/129 followed by a 11
bit programmable counter and 7 bit swallow counter
to control the 2 modulus prescaler. The reference
divider is a fully programmable 15 bit counter. The
reference frequency is a 19.44MHz TCXO.
with a latch pulse following the final data bit (see fig
7). The latch input must be held low at all other
times.
The serial bus not only programmes the modes of
operation but also enables unused sections of the
device to be powered on and off as required. This is
particularly important in a TDMA system when the
phone does not receive or transmit all of the time. An
added feature is the PCA (Power Control Assert) pin
which allows the MGCM02 to alternate between
receive and transmit modes without reloading
commands via the serial bus and gives more
accurate timing.
The synthesiser charge pumps can be programmed
to four current levels to drive the appropriate loop
filters.
The synthesisers also provide lock detect outputs.
There is also a lock detect input pin (E4) which can
be connected to the system UHF synthesiser and is
then gated with the MGCM02 lock detect to give a
combined lock detect output to the baseband
controller via Lock Detect output pin (C5). This logic
can use either the receive or transmit lock detect
which is selected via the serial bus.
Details of the serial bus are shown below. A total of 8
words can be programmed but some of these are for
test purposes only and are not required in normal
applications.
Programming
The MGCM02 features very flexible programming via
a 3 wire serial bus. Data is clocked in 24 bit words
Bit
23
X
X
X
X
X
X
X
22
X
X
X
X
X
X
X
21
X
X
X
X
X
X
X
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
Word 8
RXDIV <17:0>
TXDIV <17:0>
0
0
TLI
0
RLI
TPP
0
REFRX <14:0>
REFTX <14:0>
RPP
X
0
TPR <2:0>
TDC
RPR <2:0>
TCC RTC TCP <1:0> RCO <1:0> LDC
0
TC <3:0>
VPD LOI
VGA <2:0>
0
X
X
X
X
0
TXG <2:0>
RSS
TXC
RX
TX <1:0>
X
X
0
0
0
PCS <3:0>
LPC <1:0>
X
X
CONT <3:0>
0
CALCO <7:0>
PDF <1:0> RDC
TEST
X
Not used
RX
Receive Mode
RXDIV
Receive Synthesiser (LO2) Divide
Ratio
Transmit Synthesiser Divide Ratio
Receive Synthesiser Reference
Divide Ratio
LOI
Select low/high side LO
Transmit Gain
RSSI Control
Receive Control
Transmit Calibrate
Transmit Calibrate control - set to
1000
TXG<2:0>
RSS<2:0>
CONT<3:0>
TXC
TXDIV
REFRX
REFTX
Transmit Synthesiser Reference
Divide Ratio
TC<3:0>
RCP,TCP<1:0>
RTC,TTC
Receive, Transmit synthesiser
Charge Pump Current control
Receive, Transmit synthesiser
Charge Pump Tristate control
Receive, Transmit synthesiser
prescaler ratio
Receive, Transmit synthesiser
phase detector polarity
Receive, Transmit lock detect
invert
CALCO<3:0>
LPC
Sets transmit cut off frequency -
set to 00001100 for standard
25kHz cutoff
Set FM Audio filter cut off
frequency
Enables additional FM Audio filtering
LO Oscillator power down
Selects transmit output bias voltage
Selects receive output bias voltage
Selects VGA Mode - primarily used for
test purposes
RPR,TPR<2:0>
RPP,TPP
PDF
VPD
TDC
RDC
TLI,RLI
VGA<2:0>
LDC
TX<1,0>
PCS<2:0>
Lock Detect Select
Transmit Control
Power Control System
13
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
