MGCM01
GND
RSSI FB
AUDIO FB
AUDIO
GND
RSSI
V
DD
GND
RXI OP1
RXI OP2
RXQ OP1
RXQ OP2
PIN 1
PIN 48
RXI IP1
RXI IP2
RXQ IP1
RXQ IP2
V
DD
RX PD
GND
RX VCO
GND
TX VCO
V
DD
TX PD
MGCM01
RTUNE
VBG
RESET
PCA
SLATCH
SCLK
GND
VDD
TCXO
SDAT
LOCKDET
GND
UHF LOCK
TXQ OP1
TXQ OP2
TX FM
TXI OP1
TXI OP2
V
DD
TXI IP2
TXI IP1
GND
TXQ IP2
TXQ IP1
TP48
Figure 2 - Pin connections - top view
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
RXQ OP-
RXQ OP+
RXI OP-
RXI OP+
GND
V
DD
RSSI
GND
AUDIO
AUDIO FB
RSSI FB
GND
RXI IP+
RXI IP-
RXQ IP+
RXQ IP-
V
DD
RX PD
GND
RX VCO
GND
TX VCO
V
DD
TX PD
Type
O
O
O
O
GND
PWR
O
GND
O
I
I
GND
I
I
I
I
PWR
O
GND
I
GND
I
PWR
O
Description
Baseband receive Q output-
Baseband receive Q output+
Baseband receive I output-
Baseband receive I output+
Ground (substrate connection)
Power - RSSI/demodulator
RSSI output
Ground - RSSI/demodulator
Demodulator audio/data output
Demodulator feedback
RSSI feedback
Ground - receive section
Receive I Input+
Receive I Input-
Receive Q Input+
Receive Q Input-
Power - receive section
Rx PLL charge pump output
Ground (substrate connection)
Receive IF PLL input
Ground - synthesiser
Transmit IF PLL input
Power - synthesiser
Tx PLL charge pump output
Pin
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
UHF LOCK
TXQ OP+
TXQ OP-
TX FM
TXI OP+
TXI OP-
V
DD
TXI IP-
TXI IP+
GND
TXQ IP-
TXQ IP+
GND
LOCK DET
SDAT
TCXO
V
DD
GND
SCLK
SLATCH
PCA
RESET
V
BG
RTUNE
Type
I
O
O
O
O
O
PWR
I
I
GND
I
I
GND
O
I
I
PWR
GND
I
I
I
I
O
I
Description
UHF synthesiser lock input
Transmit Q output+
Transmit Q output-
Transmit FM output
Transmit I output+
Transmit I output-
Power - transmit section
Transmit I input-
Transmit I input+
Ground TX channel
Transmit Q input-
Transmit Q input+
Ground (substrate connection)
Synthesiser lock detect output
Serial interface, serial data in
19·44MHz reference from TCXO
Power supply - digital
Ground - digital
Serial interface clock
Serial interface latch
Power control assert
Chip master reset (active low)
Bandgap reference decoupling
Bias Ref. - connect 100kΩ to GND
Table 1 Pin descriptions
Absolute Maximum Ratings
Supply voltage (V
DD
)
Voltage applied to any pin
Operating temperature
-0·3V
to
+3·9V
-0·3V
to V
DD
+0·3V
-30°C to
+100°C
Storage temperature
Max. junction temperature
ESD (Human Body Model)
-55°C to +150°C
+150°C
2kV
2
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