Preliminary Information
Pin Description
No
1
2
3
4
MFT62330A-J
Name
Gnd
V
CC
V
CC
TX_EN
1-4
Logic
Description
Ground
Positive power supply
Positive power supply
No
50
49
48
47
Name
Gnd
V
CC
V
CC
TX_R
Logic
Description
Ground
Positive power supply
Positive power supply
CMOS
Transmitter Enable
channels 1 to 4
High = Transmitter
channels active.
Low = Transmitter
channels turned off.
Internal pull-down resistor
50kΩ.
Not Connected
NMOS
Transmitter Ready after
power-up.
Low = Transmitter not
ready.
High = Transmitter ready.
Open drain with internal
pull-up resistor 10kΩ.
Not Connected
Not Connected
5
6
TX_EN
5-8
CMOS
46
45
44
43
42
41
Gnd
Di8
Di8c
Gnd
Di7
Di7c
Gnd
Di6
Di6c
Gnd
Di5c
Di5c
Gnd
CML
CML
CML
CML
CML
CML
CML
CML
Transmitter Enable
channels 5 to 8.
High = Transmitter
channels active.
Low = Transmitter
channels turned off.
Internal pull-down resistor
50kΩ.
Ground
Ground
Data input No 8.
Data input No 8, inv.
Ground
Data input No 7.
Data input No 7, inv.
Ground
Data input No 6.
Data input No 6, inv.
Ground
Data input No 5.
Data input No 5, inv.
Ground
Not Connected
Not Connected
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Gnd
Di1c
Di1
Gnd
Di2c
Di2
Gnd
Di3c
Di3
Gnd
Di4c
Di4
Gnd
CML
CML
CML
CML
CML
CML
CML
CML
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Data input No 1, inv
Data input No 1.
Ground
Data input No 2, inv.
Data input No 2.
Ground
Data input No 3, inv
Data input No 3.
Ground
Data input No 4, inv.
Data input No 4.
Ground
Not Connected
Not Connected
Gnd
Ground
Not Connected
Not Connected
Gnd
Ground
Gnd
Ground
Not Connected
Not Connected
Gnd
Ground
9
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
