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MDS212 参数 Datasheet PDF下载

MDS212图片预览
型号: MDS212
PDF下载: 下载PDF文件 查看货源
内容描述: 12端口10 / 100Mbps以太网交换机 [12-Port 10/100Mbps Ethernet Switch]
分类和应用: 以太网局域网(LAN)标准
文件页数/大小: 111 页 / 1600 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MDS212
Description
Data Sheet
The MDS212 is a 12-port 10/100Mbps high-performance, non-blocking Ethernet switch with on-chip address
memory and address lookup engine. A single chip provides 12 - 10/100Mbps ports. The MDS212 can be utilized in
both managed and unmanaged switching applications.
The 3.2 Gbps XPipe allows a high-speed connection between two MDS212 chips, providing a optimal, low-cost,
workgroup witch with 24 10/100 Fast Ethernet ports.
In half-duplex mode, all ports support back pressure flow control to minimize the risk of losing data for long activity
bursts. In full-duplex mode, IEEE 802.3x frame based flow control is used. With full-duplex capabilities, the Fast
Ethernet ports supports 200Mbps aggregate bandwidth connections.
The MDS212 supports port trunking/load sharing on the 10/100Mbps ports. Port trunking/load sharing can be used
to group ports between interlinked switches for increased system bandwidth. Ports within a trunk must reside within
a single MDS212, such that trunks may not be configured across two switches.
The on-chip address lookup engine supports up to 2K MAC addresses and up to 256 IEEE 802.1Q Virtual LANs
(VLAN). Each port may be programmed to recognize VLANs, and will transmit frames along with their VLAN Tags,
for interoperability, to systems that support VLAN Tagging.
Each port independently collects statistical information using SNMP and the Remote Monitoring Management
Information Base (RMON – MIB). Access to these statistical counter/registers are provided via the CPU interface.
SNMP Management frames may be received and/or transmitted via the CPU interface and thus creates a complete
network management solution.
The MDS212 utilizes cost effective, high performance, pipelined SBRAM to achieve full wire speed on all ports
simultaneously. Data is buffered into memory, using 0-128 byte bursts, from the ingress ports, and transferred to an
internal transmit FIFO, before being sent from the frame memory to the egress output ports. Extremely high
memory bandwidth is therefore achieved, which allows each of the ports to be active without creating a memory
bottleneck.
The MDS212 is fabricated with 2.5 V technology, where the inputs are 3.3V tolerant and the outputs are capable of
directly interfacing to Low-Voltage TTL levels. The MDS212 is packaged in a 456-pin Ball Grid Array.
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Zarlink Semiconductor Inc.