MDS105
7.0
Port Mirroring
Data Sheet
Utilizing the 4 port mirroring control pins provides the ability to enable or disable port mirroring, select which of the
remaining 3 ports is to be mirrored, and choose whether the receive or transmit data is being mirrored. The control
for this function is shown in the following table.
Mirrored Port
Port 0 RX
Port 0 TX
Port 1 RX
Port 1 TX
Port 2 RX
Port 2 TX
Disabled
Mirror_Control [3]
1
0
1
0
1
0
0/1
Mirror_Control [2]
0
0
0
0
1
1
1
Table 2 - Port Mirroring Configuration
When enabled, port mirroring will allow the user to monitor traffic going through the switch on output Port 3. If the
port mirroring control pins MIR_CTL[3:0] are left floating, the MDS105 will operate with the port mirroring function
disabled.
When port mirroring is enabled, the user must configure Port 3 to operate in the same mode as the port it is
mirroring (autonegotiation, duplex, speed, flow control).
Mirror_Control [1]
0
0
0
0
1
1
1
Mirror_Control [0]
0
0
1
1
0
0
1
8.0
Power Saving Mode in MAC
The MDS105 was designed to be power efficient. When the internal MAC sections detect that the external port is
not receiving or transmitting packets, it will shut off and conserve power. When new packet data is loaded into the
output transmit FIFO of a MAC in power saving mode, the MAC will return to life and begin operating immediately.
When the MAC is in power saving mode and new packet data is received on the RMII, the MAC will return to life
and receive data normally into the receive FIFO. This wakeup occurs when the MAC sees the Carrier Sense Data
Valid (CRS_DV) signal asserted.
Using this method, the switch will turn off all MAC sections during periods when there is no network activity (at
night, for example), and save power. For large networks this power savings could be large. To achieve the
maximum power efficiency, the designer should use a physical layer transceiver that utilizes “Wake-On-LAN”
technology.
9.0
EEPROM I
2
C Interface
A simple 2 wire serial interface is provided to allow the configuration of the MDS105 from an external EEPROM.
The MDS105 utilizes a 1 K bit EEPROM with an I
2
C interface.
12
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
