MA5104
T
AVAVW
ADDRESS
T
AVWH
T
AVWL
(4)
T
WHAV (3)
T
WLWH (2)
WE
T
AXQX
T
WLQZ
T
ELWL
(7)
T
WLQH
(5)
(6)
DATA OUT
HIGH
IMPEDANCE
T
DVWH
DATA IN
DATA VALID
T
WHDX
T
ELWH
CS
1.
WE
must be high during all address transitions.
2. A write occurs during the overlap (T
WLWH
) of a low
CS,
a high CE and a low
WE.
3. T
WHAV
is measured from either
CS
or
WE
going high or CE going low, whichever is the earlier, to the end
of the write cycle.
4. If the
CS
low transition occurs simultaneously with, or after, the
WE
low transition, the output remains in
the high impedance state.
5. DATA OUT is the write data of the current cycle, if selected.
6. DATA OUT is the read data of the next address,if selected.
7. T
ELWL
must be met to prevent memory corruption.
Figure 12: Write Cycle
6
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
