MA2910
Instruction Based
Address Based
A Register at the Microprogram Memory output contains
the microinstruction being executed. The Microprogram
Memory and MA2901 delay are in series. Conditional
branches are executed on the same cycle as the ALU
operation generating the condition.
The Register at the MA2910 output contains the
microinstruction being executed. The Microprogram Memory
and MA2901 are in series within the critical path. This
architecture is of comparable speed to the Instruction Based
architecture, but requires fewer register bits, since only the
address (typically 10 to 12 bits) is stored instead of the
instruction.
Figure 20: Instruction Based
Figure 22: Address Based
Data Based
The Status Register provides conditional branch control
based on results of the previous ALU cycle. The Microprogram
memory and the MA2901 are in series within the critical path.
Two Level pipeline Based
This architecture provides the highest possible speed. It is,
however, more difficult to program as the selection of a
microinstruction occurs two instructions ahead of its execution.
Figure 21: Data Based
Figure 23: Two Level Pipeline Based
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