MA2901
In the shift up mode, the RAM
3
buffer is enabled and the
RAM
0
multiplexer input is enabled. Likewise, in the shift down
mode, the RAM
0
buffer and RAM
3
input are enabled. In the no-
shift mode, both buffers are in the high-impedance state and
the multiplexer inputs are not selected. The shifter is controlled
from the I
6
, I
7
and I
8
microinstruction inputs as defined in Figure
4.
Similarly, the Q register is driven from a 3-input
multiplexer. In the non-shift mode, the multiplexer enters the
ALU data into the Q register. In either the shift-up or shift-down
mode, the multiplexer selects the Q register data appropriately
shifted up or down. The Q shifter also has two ports; one is
labeled Q
0
and the other is Q
3
. The operation of these two
ports is similar to the RAM shifter and is also controlled from I
6
,
I
7
and I
8
as shown in Figure 4.
The clock input shown in Figure 1 controls the RAM, the Q
resister and the A and B data latches. When enabled, data is
clocked into the Q register on the LOW-to-HlGH transition of
the clock. When the clock input is HIGH, the A and B latches
are open and will pass whatever data is present at the RAM
outputs. When the clock input is LOW, the latches are closed
and will retain the last data entered. If the RAM-EN is enabled
new data will be written into the RAM file (word) defined by the
B address field when the clock input is LOW.
SOURCE OPERANDS & ALU FUNCTION
Any one of eight source operand pairs can be selected by
instruction inputs lo, l
1
and I
2
for use by the ALU; instruction
inputs I
3
, I
4
, and I
5
then control function selection for the ALU -
five logic and three arithmetic functions. In the arithmetic
mode, the carry input (Cn) also affects the ALU functions; the
carry input has no effect on the ‘F’ result in the logic mode.
These control parameters (I
6
- l
0
and Cn) are summarised in
Figure 5 to completely define the ALU/source operand
functions.
The ALU functions can also be examined on a task basis:
that is, add, subtract, AND, OR, and so on. Again, in the
arithmetic mode, the carry input still affects the result, whereas
in the logic mode it will not. Figures 6 and 7, respectively,
define the various logic and arithmetic functions of the ALU;
both carry states (Cn = 0 / Cn = 1) are defined in the function
matrices.
Microcode
I
8
L
L
L
L
H
H
H
H
I
7
L
L
H
H
L
L
H
H
I
6
L
H
L
H
L
H
L
H
Octal
Code
0
1
2
3
4
5
6
7
RAM Function
Shift
X
X
None
None
Down
Down
Up
Up
Load
None
None
F
→
B
F
→
B
F/2
→
B
F/2
→
B
2F
→
B
2F
→
B
Q-Reg Function
Shift
None
X
X
X
Q/2
→
Q
X
Up
X
Load
F
→
Q
None
None
None
F
None
2Q
→
Q
None
Y
Output
F
F
A
F
-
F
F
F
RAM Shifter
RAM
0
X
X
X
X
F
0
F
0
IN
0
IN
0
RAM
3
X
X
X
X
IN
3
IN
3
F
3
F
3
Q Shifter
Q
0
X
X
X
X
Q
0
Q
0
IN
3
X
Q
3
X
X
X
X
IN3
X
Q
3
Q
3
X = Don't Care. Electrically, the shift pin is a TTL input internally connected to a TRI-STATE output which is in the high-impedance state.
B = Register addressed by 8 inputs. Up is towards MSB, Down is towards LSB.
Figure 4: ALU Destination Control
I
2,1,0
Oc ta l
ALU Source
/ALU
Function
C n =L
R plus S
C n =H
Cn=L
S minus R
C n =H
C n =L
R minus S
C n =H
R or S
R and S
RN and S
R EX-OR S
R EX NOR S
0
A,Q
A+Q
A+Q+1
Q-A-1
Q-A
A-Q-1
A-Q
A
V
Q
A
Λ
Q
AN
Λ
Q
A
∇
Q
AN
∇
QN
1
A,B
A+B
A+B+1
B-A-1
B-A
A-B-1
A-B
A
V
B
A
Λ
B
AN
Λ
B
A
∇
B
AN
∇
BN
2
0,Q
Q
Q +1
Q -1
Q
-Q-1
-Q
Q
0
Q
Q
Q
3
0,B
B
B+1
B-1
B
-B-1
-B
B
0
B
B
B
4
0,A
A
A+1
A-1
A
-A-1
-A
A
0
A
A
A
5
D,A
D+A
D+A+1
A - D1
A-D
D - A -1
D-A
D
V
A
D
Λ
A
DN
Λ
A
D
∇
A
DN
∇
AN
6
D,Q
D+Q
D+Q+1
Q-D-1
Q-D
D-Q-1
D-Q
D
V
Q
D
Λ
Q
DN
Λ
Q
D
∇
Q
DN
∇
QN
7
D,0
D
D+1
-D - 1
-D
D-1
D
D
0
0
D
DN
O ct al
I
5,4,3
0
1
2
3
4
5
6
7
+ = plus; - = minus;
V
= OR;
Λ
= AND;
∇
= EX-OR
Figure 5: Source Operand and ALU Function Matrix
4
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
