MA2901
PIN DESCRIPTION
Name
A
0-3
B
0-3
I
0-8
I/O
I
I
Description
The four address inputs to the register stack used to select one register whose
contents are displayed through the A port
The four address inputs to the register stack used to select one register whose
contents are displayed through the B port and into which new data can be written
when the clock goes LOW
The nine instruction control lines. Used to determine what data sources will be
applied to the ALU(I
0,1,2
), what function the ALU will perform (I
3,4,5
), and what
data is to be deposited in the Q-register or the register stack (I
6,7,8
)
The shift line at the MSB of the Q-register (Q
3
) and the register stack (RAM
3
).
Electrically these lines are three-state outputs connected to TTL inputs internal to
the device. When the destination code on I
6,7,8
indicates an up shift (Octal 6 or 7)
the three state outputs are enabled and the MSB of the Q-register is available on
the Q
3
pin and the MSB of the ALU output is available on the RAM
3
pin.
Otherwise, the three state outputs are electrically OFF (high impedance) and the
pins are electrically LS-TTL inputs. When the destination code calls for a down
shift, the pins are used as the data inputs to the MSB of the Q-register (Octal 4)
and RAM (Octal 4 or 5)
Shift lines like Q
3
and RAM
3
, but at the LSB of the Q-register and RAM. These
pins are tied to the Q
3
and RAM
3
pins of the adjacent device to transfer data
between devices for up and down shifts of the Q-register and ALU data.
Direct data inputs. A four-bit data field which may be selected as one of the ALU
data sources for entering data into the device D
0
is the LSB
The four data outputs. These are three-state output lines. When they are enabled,
they display either the four outputs of the ALU or the data on the A-port of the
register stack, as determined by the destination code I
6,7,8.
Output enable. When OEN is HIGH, the Y outputs are OFF; when OEN is LOW, the
Y outputs are active (HIGH or LOW)
The carry generate and propagate outputs of the internal ALU. These signals are
used with the MA2901 for carry lookahead.
Overflow. This pin is logically the Exclusive OR of the carry-in and carry-out of the
MSB of the ALU. At the most significant end of the word, this pin indicates that the
result of an arithmetic two’s complement operation has overflowed into the sign-bit
This is an open collector output which goes HIGH(OFF) if the data on the four ALU
outputs F
0-3
are all LOW. In positive logic, it indicates that the result of the ALU
operation is zero
The most significant ALU output bit.
The carry-in to the internal ALU.
The carry-out of the ALU internal ALU.
The clock input. The Q-register and register stack outputs change on the clock
LOW - to HIGH transition. The clock LOW time is internally the write enable to the
16 x 4 RAM which compromises the “master” latches of the register stack. While
the clock is LOW, the “slave” latches on the RAM outputs are closed, storing the
data previously on the RAM outputs. This allows synchronous master-slave
operation of the register stack.
Figure 8: Pin Description
I
Q
3
RAM
3
I/O
Q
0
RAM
0
D
0-3
Y
0-3
OEN
GN,PN
OVR
I/O
I
O
I
O
O
F=0
O
F
3
C
n
C
n
+ 4
CP
O
I
O
I
6
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