FEBRUARY 1995
MA2901
DS3576-3.3
MA2901
RADIATION HARD 4-BIT MICROPROCESSOR SLICE
The MA2901 is an industry standard 4-bit microprocessor
slice It provides a set of ALU functions selected by microcode
data applied to the inputs. The device is cascadable to handle
any word length. It can be used as a building block in the
construction of microcomputers and controllers tailored to
meet specialised applications.
Dual Address Architecture
Machine cycles are saved by simultaneous, independent
access to two working registers.
ALU has Eight Functions
Operations performed are addition, two subtractions and five
logic functions on two source operands.
Four State Flags
Zero, negative, carry and overflow.
Left / Right Shift is Independent of ALU
Only one cycle taken for add and shift operations.
Expandable
Any number of MA2901 units can be connected together to
achieve longer word lengths.
Micro Programmable
Three groups, each of three bits, for ALU function, source
operand and destination control.
OPERATION
A detailed block diagram of the microprogrammable
microprocessor structure is shown in figure 1. The circuit is a
four-bit slice, cascadable to any number of bits. Therefore, all
data paths within the circuit are four bits wide. The two key
elements in the figure 1 are the 16-word by 4-bit 2-port RAM
and the high speed ALU.
Data from any of the 16 words of the Random Access
Memory (RAM) can be read from the A-port of the RAM as
controlled by the 4-bit A-address field input. Likewise, data
from any of the 16 words of the RAM as defined by the B-
address field input can be simultaneously read from the B-port
of the RAM. The same code can be applied to the A-select field
and B-select field in which case the identical file data will
appear at both the RAM A-port and B-port outputs
simultaneously.
When enabled by the RAM write enable (RAM EN), new
data is always written into the file (word) defined by the B-
address field of the RAM. The RAM data input field is driven by
a 3-input multiplexer. This configuration is used to shift the
ALU output data (F) if desired. This three-input multiplexer
scheme allows the data to be shifted up one bit position,
shifted down one bit position, or not shifted in either direction.
The RAM A-port data outputs and RAM B-port data outputs
drive separate 4-bit latches. These latches hold the RAM data
while the clock input is LOW. This eliminates any possible race
conditions that could occur while new data is being written into
the RAM.
The high-speed Arithmetic Logic Unit (ALU) can perform
three binary arithmetic and five logic operations on the two 4-
bit input words R and S. The R input field is driven from a 2-
input multiplexer, while S input field is driven from a 3-input
multiplexer. Both multiplexers also have an inhibit capability;
that is, no data is passed. This is equivalent to a “zero” source
operand.
The ALU R-input multiplexer has the RAM A-port and the
direct data inputs (D) connected as inputs. Likewise, the ALU
S-input multiplexer has the RAM A-port, the RAM B-port and
the Q register connected as inputs.
FEATURES
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Fully Compatible with Industry Standard 2901
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CMOS SOS Technology
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High SEU Immunity and Latch-up Free
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High Speed
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Low Power
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