MA17503
4.5 DMA SUPPORT
4.7 TIMER OPERATIONS
DMA data transfers are performed over the system AD bus
under the control of the lU DMA interface logic. The user
signals that DMA requests will be honored by setting the DMAE
output high via the DMAE internal I/O command. The DMA
controller may request use of the AD bus by pulling DMARN
low, but, unless DMAE is high, all such requests will be ignored.
DMARN is acknowledged by raising DMAKN low. This occurs
at the first SYNCLKN high-to-low transition after DMARN is
pulled low.
When a DMA request is acknowledged (DMAKN low), DDN
is dropped low to direct the system data bus transceivers to
drive the local AD bus, and CDN is dropped low to disable the
control signal buffers. (It is necessary to use transceivers to
buffer the control bus if a shared MMU(BPU) architecture is
used, to allow the sharing device access to the MMU(BPU)
functions).
Interval Timers A and B, the Trigger-Go Counter and the
Bus-Fault timer are all implemented in the Interrupt Unit.
4.7.1 Timers A and B
Timer A is clocked by the TCLK input (which is internally
synchronised to SYNCLKN), whereas Timer B is clocked by an
internally generated TCLK/10 (also internally synchronized to
SYNCLKN). TCLK is required to be a 100KHz pulse train by
MIL-STD-1750A. If they are allowed to overflow. Timers A and
B will set level 7 and level 9 interrupt requests, respectively.
Each timer can be read, loaded, started, and stopped via
internal I/O commands.
External control of Timers A and B can be accomplished by
asserting the DTIMERN input. When DTIMERN is low, both
timers will halt and all internally decoded internal I/O
commands which would change their state are disabled
(asserting DTIMERN low also disables DMA accesses by
driving DMAE low and DMAKN high). Raising DTlMERN high
allows normal operations to resume where they left off.
When the DMA controller relinquishes control of the AD bus
(by raising DMARN high), DMA operations are ended by raising
DMAKN high at the next SYNCLKN high-to-low transition, and
DDN and CDN then resume normal operation.
4.7.2 Trigger-Go Counter
4.6 HOLD SUPPORT
The Trigger-Go Counter is clocked by the TGCLK input.
DTlMERN low disables and enables counter operations in the
same way as Timers A and B. When the Trigger-Go counter
overflows, the output discrete TGON drops low and remains
low until the counter is reset via the “GO’’ internal l/Ocommand.
The Hold interface is handled by the Execution Unit, but the
Hold acknowledge (HLDAKN) line is monitored by the Interrupt
Unit. When HLDAKN is active, the Interrupt Unit lowers DDN
and CDN, resets and disables the Bus-Fault decoding (bits 4-
6). When the Hold state is terminated, DDN and CDN resume
normal operation.
4.7.3 Bus-Fault Timer
This on-chip watchdog timer is provided to monitor all bus
operations to ensure timely completion. This hardware timeout
circuit is enabled at the start of each memory and l/O transfer
(DSN high-to-low transition), and is reset on the following
SYNCLKN high-to-low transition (an external ready (RDYN)
must have been received by the Execution Unit for this to
occur).
lf this circuit is not reset within a minimum of one TCLK
period or a maximum of two TCLK periods, either bit 3 (if a
memory transaction) or bit 5 (if an l/O transaction) of the FT
register is set. This causes the current MlL-STD-1750A
instruction to be aborted as discussed above. This feature can
be disabled externally by pulling DTON low and is not available
during DMA or the Hold state (DMAKN or HLDAKN low).
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