MA17503
BIT
1
Test Coverage
Microcode Sequencer
IB Register Control
Barrel Shifter
Byte Operations and Flags
Temporary Registers (T0 - T7)
Macrocode Flags
MuItlply
Divide
Interrupt Unit - MK, Pl, FT
Enable/Disable Interrupts
Status Word Control
User Flags
General Registers (R0 - R15)
Timer A
Timer B
BIT Pass/Fail Overhead
BIT Fail Codes (FT13, 14, 15)
100
Cycles
221
2
101
166
3
111
214
4
110
154
5
111
763
-
-
26
Note:
BIT pass is indicated by all zeros in FT bits 13, 14, and 15
Table 4: MAS281 BIT Summary
4.2 INSTRUCTION EXECUTION
The MAS281 chip set will begin instruction execution upon
the completion of initialization. The instruction execution
operations that involve the Interrupt Unit are: (1) internal CPU
cycles, (2) memory transfers, and (3) input/output transfers.
Instruction execution can be interrupted at the end of any
individual machine cycle by a DMA request (DMARN low with
DMAE high) or at the conclusion of any given instruction by an
lnterrupt or Hold state request.
4.2.1 Internal CPU Cycles
Microcode controlled lU functions are classified as internal
CPU cycles. The lU interprets the three microcode bits, 4, 5,
and 6, as a three bit instruction used for control of the FT,
internal DMA interface, NPU discrete, and the interrupt priority
vector code. The command is latched into the lU at the
SYNCLKN high-to-low transition and decoded into control
signals if INTREN is low. During these machine cycles,
SYNCLKN is six (EU)OSC periods long. During internal CPU
cycles, DSN and M/lON are held high by the Execution Unit,
causing the lU to hold DDN high. Microcode bits 4, 5, and 6 are
not latched or decoded during DMA or the Hold state (DMAKN
or HLDAKN low).
4.2.2 Memory Transfers
The IU takes a passive role during memory transfers, i.e., it
only controls the DDN signal. Microcode bits 4, 5, and 6 are
latched by the SYNCLKN high-to-low transition then bits 5 and
6 are decoded to control the DDN control signal in concert with
DSN. lf bits 5 and 6 are high (indicating a write), DSN is kept
from affecting DDN, which remains high for the entire cycle. If
either bit 5 or 6 is low, DSN is allowed to control DDN, which
becomes a delayed version of DSN.
4.2.3 Input/Output Transfers
The IU monitors all AD Bus traffic and controls the DDN
output as specified. During cycles where M/ION is low, the IU
decodes the address/command portion (SYNCLKN high) of the
machine cycle. If one of the commands listed in Table 2 is
encountered, the specific action takes place at the following
SYNCLKN high-to-low transition; the exceptions being “GO”
and “RCW”. “GO” resets the Trigger-Go Timer at the SYNCLKN
low-to-high transition and “RCW” drops CONFWN low during
DSN low.
The read and write status word commands (“RSW”,
“WSW’’) cause lRDYN to drop low to complete the EU/
MMU(BPU) machine cycle. IU decoded l/O command cycles
are six (EU)OSC periods long (except for “RCW’’, there are five
(EU)OSC periods).
4.3 INTERRUPT SERVICING
Nine user interrupt inputs and one dedicated input (OVIN)
are provided for programmed response to asynchronous
system events. A low on any of these inputs will be detected at
the high-to-low transition of SYNCLKN and latched into the Pl
register on the following SYNCLKN high-to-low transition (with
the exception of INT02N which is latched into Pl when lNT02N
is first detected). This always occurs whether interrupts are
enabled or disabled, or whether specific interrupts are masked
or unmasked. (Because INT02N is captured asynchronously, it
is possible under rare conditions for the PI bit 2 to remain set
after INT02N has been serviced, causing double servicing of
the one interrupt. To prevent this, bit 2 of the PI should be
cleared at the end of the user service routine).
10
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