MA2901
AC ELECTRICAL CHARACTERISTICS
Read-Modify-Write Cycle (from selection of A,B registers to end of a cycle
40ns
Maximum Clock Frequency to shift Q(50% duty cycle, I = 432 or 632)
25MHz
Minimum Clock LOW time
20ns
Minimum Clock HIGH time
20ns
Minimum Clock Period
40ns
Note: 1. These timings are applied during functional tests and are not routinely measured.
Figure 12: Cycle Time and Clock Characteristics
To Output
From Input
A,B Address
D
C
n
I
0,1,2
I
3,4,5
I
6,7,8
A Bypass ALU(I=2xx)
Clock
Note: All timings in ns
Y
65
55
60
70
60
45
45
55
F
3
55
40
40
50
45
-
-
50
C
n
+ 4
60
50
35
55
50
-
-
55
G,P
55
50
-
55
45
-
-
50
F=0
70
65
55
70
65
-
-
50
OVR
65
55
35
55
50
-
-
55
RAM
0
RAM
3
65
55
50
65
65
30
-
55
Q
0
Q
3
-
-
-
-
-
30
-
35
Figure 13: Combinational Propagation Delays
Input
CP:
Set-up Time
Before L
→
H
30
No change
40
40
45
45
No change
15
Hold Time
After L
→
H
-
5
0
0
0
0
10
10
Set-up Time
Hold Time
Before H
→
L
After H
→
L
A,B Source Address
25
5
B Destination Address
25
No change
D
-
-
C
n
-
-
I
0,1,2
-
-
I
3,4,5
-
-
I
6,7,8
10
No change
RAM
0,3,
Q
0,3
-
-
MIL-STD-883, method 5005, subgroups 9, 10, 11
Note:
1. VDD = 5V
±10%,
over full operational temperature range
2. CL = 50 pF
Figure 14: Set-up and Hold Times Relative to Clock (CP) Input
8
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
