MA17503
3.9 TIMER CONTROL
4.0 OPERATING MODES
These Timer Control inputs allow external control of Timers
A and B, the Trigger-Go Counter, and the Bus Fault Timeout
circuitry.
The following discussions detail the MAS281 chip set
operating modes from the perspective of the Interrupt Unit. The
MAS281 operating modes involving the MA17503 are: (1)
initialization, (2) instruction execution, (3) interrupt servicing,
(4) fault servicing, (5) DMA support, (6) Hold support, and (7)
timer operations.
3.9 1 Disable Timers (DTIMERN)
Input. A low to this input disables Timers A and B and the
Trigger-Go counter, and also disables DMA access by forcing
DMAE low and DMAKN high. Raising DTIMERN high causes
Timers A and B and the Trigger-Go counter to resume counting
where they were stopped, and also allows normal DMA
operations.
4.1 INITIALISATION
A microcoded initialisation sequence is executed by the
chip set in response to a hardware reset. This routine, as
applicable to the lnterrupt Unit, disables and masks interrupts,
zeroes the Fault register, performs the MAS281 Integrated
Built-ln Test (BIT), raises the Start-Up ROM enable discrete
(SURE), clears and starts timers A and B, resets the Trigger-Go
counter, and disables DMA access. The resulting initialised
state of the MA17503 is listed in Table 3.
The microcoded BIT exercises all legal microinstruction bit
combinations and tests all internally accessible structures of
the MAS281 chip set. For the Interrupt Unit this includes the
MK, Pl, and FT registers, Interrupt Enable/Disable, and Timers
A and B. Table 4 details the tests performed by each of the five
BlT routines.
If any part of BIT fails, an error code identifying the failed
subroutine is loaded into FT bits 13-15, BlT is aborted with NPU
left in the low state, initialization is completed, and instruction
execution begins at address zero. The coding of the BIT results
is shown in Table 4.
NOTE: To complete initialization and pass BIT, interrupt
and fault inputs must be high for the duration of the initialization
routine. ln addition, timers A and B must be clocked for BlT
success.
3.9.2 Disable Bus-Fault Timeout (DTON)
Input. A low to this input will reset and disable the Busfault
timeout circuitry.
3.10 DISCRETES
Four discrete outputs are provided for system use, all of
which are enabled or disabled or both via internal l/O
commands.
3.10.1 Trigger-Go Timer Overflow (TGON)
Output. This output drops low whenever the Trigger-Go
counter overflows (rolls over to 0000). lt returns high when the
Trigger-Go counter is reset by software using the GO internal
l/O command.
3.10.2 Normal Power-Up Indicator (NPU)
Output. This output is brought low via internal I/O command
during module initialization as the first step of BlT. lf BIT is
completed successfully, NPU is raised high via microcode, and
remains high until reset by software via the RNS internal I/O
command.
Item
Status
START-UP ROM ENABLE (SURE)
Fault (FT)
Pending Interrupt (Pl)
Mask (MK)
Interrupts
DMA Access
Timer A
Zeroed
Zeroed
Zeroed
Disabled
Output. This output is used to enable an externally
implemented Start-Up ROM. SURE is brought high via the
execution of the ESUR internal l/O command (done by
microcode during initialization or by software), and remains
high until it is reset by software by using the DSUR internal l/O
command. While SURE is high, all memory reads shall access
main memory. This feature is utilized via the MOV instruction to
effect a non-volatile memory program transfer to faster
program execution RAM.
Disabled
Reset and Started
Reset and Started
Reset and Started
Timer B
Trigger-Go Timer
Table 3: Interrupt Initialisation State
CONFIGURATION WORD ENABLE (CONFWN)
Output. This output is brought low during the data portion of
an RCW (Read Configuration Word) internal l/O operation. lt is
used as an output enable strobe for the externally implemented
Configuration Register. Because RCW is an internal I/O
command, the read cycle is a fixed six (EU)OSC cycles and is
terminated by IRDYN low. RDYN must not be asserted during
execution of this command.
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